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Reconfigurable five-layer three-dimensional integrated memory-on-logic synthetic aperture radar processor

Reconfigurable five-layer three-dimensional integrated memory-on-logic synthetic aperture radar processor

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In this study, the authors present a floating-point synthetic aperture radar processor that achieves a power efficiency of 18.0 mW/GFlop in simulation through the use of three-dimensional (3D) integration and reconfiguration of the data path. The reconfiguration reduces the number of arithmetic units required in every processing element (PE) from 24 down to 10. The processor uses a 3D integrated memory that reduces the memory power consumption by 70% when compared to a 2D memory. The system processes a SAR image using a two-tier 3D integrated PE, which when compared to an equivalent 2D PE decreases the power consumed in the interconnect of each PE by 15.5% and the footprint by 49.2%, and allows the PE to operate 7.1% faster in simulation. Additionally, by using 3D integration in the memory one can reduce the power consumption of the memory by 70%. Furthermore, the authors show how the 3D aspects of the processor can be realised by using 2D tools, when used in conjunction with the proposed through-silicon via assignment algorithm.

References

    1. 1)
      • Hein, C., Pridgen, J., Kline, W.: `RASSP virtual prototyping of DSP systems', Design Automation Conf. DAC 97, 1997, p. 492–497.
    2. 2)
      • M. Jin , C. Wu . SAR correlation algorithm which accommodates large-range migration. IEEE Trans. Geosci. Remote Sens. , 6 , 592 - 597
    3. 3)
    4. 4)
      • Vignon, A., Cosemans, S., Dehaene, W., Marchal, P., Facchini, M.: `A novel dram architecture as a low leakage alternative for sram caches in a 3d interconnect context', Design, Automation and Test in Europe Conf. Exhibition 2009, DATE ’09, April 2009, p. 929–933.
    5. 5)
      • Dong, X., Wu, X., Sun, G., Xie, Y., Li, H., Chen, Y.: `Circuit and microarchitecture evaluation of 3d stacking magnetic ram (mram) as a universal memory replacement', Proc. 45th Annual Design Automation Conf., DAC ’08, 2008, p. 554–559.
    6. 6)
      • Dong, X., Xie, Y.: `System-level cost analysis and design exploration for three-dimensional integrated circuits (3d ics)', Proc. 2009 Asia and South Pacific Design Automation Conf., ASP- DAC ’09, 2009, p. 234–241.
    7. 7)
    8. 8)
    9. 9)
      • Thorolfsson, T., Gonsalves, K., Franzon, P.D.: `Design automation for a 3dic fft processor for synthetic aperture radar: a case study', Proc. 46th Annual Design Automation Conf., DAC ’09, 2009, p. 51–56.
    10. 10)
      • Thorolfsson, T., Moezzi-Madani, N., Franzon, P.D.: `A low power 3d integrated fft engine using hypercube memory division', Proc. 14th ACM/IEEE Int. Symp. on Low Power Electronics and Design, ISLPED ’09, 2009, p. 231–236.
    11. 11)
    12. 12)
      • Koyanagi, M., Fukushima, T., Tanaka, T.: `Three-dimensional integration technology and integrated systems', 2009 Asia and South Pacific Design Automation Conf. ASP-DAC '09, January 2009, p. 409–415.
    13. 13)
      • Madan, N., Zhao, L., Muralimanohar, N.: `Optimizing communication and capacity in a 3d stacked reconfigurable cache hierarchy', Proc. 2009 Int. Symp. on High-Performance Computer Architecture, HPCA ’09, February 2009, p. 262–274.
    14. 14)
    15. 15)
      • V. Jain , S. Bhanja , G. Chapman , L. Doddannagari . (2005) A highly reconfigurable computing array: Dsp plane of a 3d heterogeneous soc.
    16. 16)
    17. 17)
    18. 18)
      • Patti, R.: `Interlocking conductor method for bonding wafers to produce stacked integrated circuits', US, 6 838 774, 4 January 2005.
    19. 19)
      • Tezzaron: ‘Wafer stack with super-contacts’. Available at http://www.tezzaron.com/about/PhotoAlbum/Products/Wafer_Pair_Super-Contacts.html.
    20. 20)
      • Hentschke, R., Flach, G., Pinto, F., Reis, R.: `Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing', Proc. 19th Annual Symp. on Integrated Circuits and Systems Design., SBCCI ’06, 2006, p. 220–225.
    21. 21)
      • Das, S., Chandrakasan, A., Reif, R.: `Design tools for 3-d integrated circuits', Proc. 2003 Conf. on Asia South Pacific Design Automation, ASPDAC, 2003, p. 53–56.
    22. 22)
      • Goplen, B., Sapatnekar, S.: `Efficient thermal placement of standard cells in 3D ICs using a force directed approach', Int. Conf. on Computer Aided Design 2003, ICCAD-2003, 2003, p. 86–89.
    23. 23)
      • Cong, J., Wei, J., Zhang, Y.: `A thermal-driven floorplanning algorithm for 3D ICs', IEEE/ACM Int. Conf. on Computer Aided Design, 2004, ICCAD-2004, 2004, p. 306–313.
    24. 24)
      • Cong, J., Luo, G.: `A multilevel analytical placement for 3d ics', Asia and South Pacific Design Automation Conf., 2009, ASP-DAC 2009, January 2009, p. 361–366.
    25. 25)
      • Cong, J., Luo, G., Wei, J., Zhang, Y.: `Thermal-aware 3d ic placement via transformation', Asia and South Pacific Design Automation Conf., 2007, ASP-DAC ’07, January 2007, p. 780–785.
    26. 26)
      • Karypis, G., Kumar, V.: `Multilevel k-way hypergraph partitioning', Proc. 36th Design Automation Conf. 1999, 1999, p. 343–348.
    27. 27)
    28. 28)
      • Micron: ‘The micron system-power calculator’. Available at http://www.micron.com/support/parLinfo/powercalc.
    29. 29)
    30. 30)
    31. 31)
      • Arakawa, F., Yoshinaga, T., Hayashi, T.: `An embedded processor core for consumer appliances with 2.8gflops and 36m polygons/s fpu', IEEE Int. Solid-State Circuits Conf. 2004, ISSCC 2004, Digest of Technical Papers, February 2004, 1, p. 334–531.
    32. 32)
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