Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation

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Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation

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Published

Magnetic random access memory (MRAM) has been considered as a promising memory technology because of its attractive properties such as non-volatility, fast access, zero standby leakage and high density. Although integrating MRAM with complementary metal-oxide-semiconductor (CMOS) logic may incur extra manufacturing cost because of the hybrid magnetic-CMOS fabrication process, it is feasible and cost-effective to fabricate MRAM and CMOS logic separately and then integrate them using 3D stacking. In this work, we first studied the MRAM properties and built an MRAM cache model in terms of performance, energy and area. Using this model, we evaluated the impact of stacking MRAM caches atop microprocessor cores and compared MRAM against its static random access memory (SRAM) and dynamic random access memory (DRAM) counterparts. Our simulation result shows that MRAM stacking can provide competitive instruction-per-cycle (IPC) performance with a large reduction in power consumption.

Inspec keywords: SRAM chips; microprocessor chips; MRAM devices; CMOS memory circuits

Other keywords: architecture level evaluation; stacking magnetic random access memory atop microprocessors; MRAM; power consumption; complementary metal oxide semiconductor; instruction-per-cycle; SRAM; IPC; microprocessor cores; CMOS

Subjects: Microprocessor chips; Storage on stationary magnetic media; Microprocessors and microcomputers; Magneto-acoustic, magnetoresistive, magnetostrictive and magnetostatic wave devices; Semiconductor storage; Memory circuits

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