© The Institution of Engineering and Technology
Magnetic random access memory (MRAM) has been considered as a promising memory technology because of its attractive properties such as non-volatility, fast access, zero standby leakage and high density. Although integrating MRAM with complementary metal-oxide-semiconductor (CMOS) logic may incur extra manufacturing cost because of the hybrid magnetic-CMOS fabrication process, it is feasible and cost-effective to fabricate MRAM and CMOS logic separately and then integrate them using 3D stacking. In this work, we first studied the MRAM properties and built an MRAM cache model in terms of performance, energy and area. Using this model, we evaluated the impact of stacking MRAM caches atop microprocessor cores and compared MRAM against its static random access memory (SRAM) and dynamic random access memory (DRAM) counterparts. Our simulation result shows that MRAM stacking can provide competitive instruction-per-cycle (IPC) performance with a large reduction in power consumption.
References
-
-
1)
-
Desikan, R., Lefurgy, C.R., Keckler, S.W., Burger, D.: `On-chip MRAM as a high-bandwidth low-latency replacement for DRAM physical memories', Tech., 2002.
-
2)
-
Chen, Y., Wang, X., Li, H., Liu, H., Dimitrov, D.V.: `Design margin exploration of spin-torque transfer RAM (SPRAM)', Proc. Int. Symp. on Quality Electronic Design, 2008, p. 684–690.
-
3)
-
Qureshi, M.K., Srinivasan, V., Rivers, J.A.: `Scalable high performance main memory system using phase-change memory technology', Proc. Int. Symp. on Computer Architecture, 2009, p. 24–33.
-
4)
-
Krewel, K.: `Alpha ev7 processor: a high-performance tradition continues', Microprocessor Report, 2005.
-
5)
-
Kawahara, T., Takemura, R., Miura, K.: `2 Mb spin-transfer torque RAM (SPRAM) with bit-by-bit bidirectional current write and parallelizing-direction current read', Proc. Int. Solid-State Circuits Conf., 2007, p. 480–617.
-
6)
-
Tanizaki, H., Tsuji, T., Otani, J.: `A high-density and high-speed 1T-4MTJ MRAM with voltage offset self-reference sensing scheme', Proc. Asian Solid-State Circuits Conf., 2006, p. 303–306.
-
7)
-
Tsuchida, K., Inaba, T., Fujita, K.: `A 64 Mb MRAM with clamped-reference and adequate-reference schemes', Proc. Int. Solid-State Circuits Conf., 2010, p. 268–269.
-
8)
-
Schechter, S., Loh, G.H., Straus, K., Burger, D.: `Use ECP, not ECC, for hard failures in resistive memories', Proc. Int. Symp. on Computer Architecture, 2010, p. 141–152.
-
9)
-
Zhou, P., Zhao, B., Yang, J., Zhang, Y.: `A durable and energy efficient main memory using phase change memory technology', Proc. Int. Symp. on Computer Architecture, 2009, p. 14–23.
-
10)
-
Loi, G.L., Agrawal, B., Srivastava, N.: `A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy', Proc. Design Automation Conf., 2006, p. 991–996.
-
11)
-
Hosomi, M., Yamagishi, H., Yamamoto, T.: `A novel nonvolatile memory with spin torque transfer magnetization switching: spin-RAM', Proc. Int. Electron Devices Meeting, 2005, p. 459–462.
-
12)
-
Desikan, R., Keckler, S., Burger, D.: `Assessment of MRAM technology characteristics and architectures', Tech., 2002.
-
13)
-
W. Reohr ,
H. Honigschmid ,
R. Robertazzi
.
Memories of tomorrow.
IEEE Circuits Devices Mag.
,
5 ,
17 -
27
-
14)
-
The MOSIS Service, available at: http://www.mosis.com/technical/designrules/scmos/, 2008.
-
15)
-
Bienia, C., Kumar, S., Singh, J.P., Li, K.: `The PARSEC benchmark suite: characterization and architectural implications', Proc. Int. Conf. on Parallel Architectures and Compilation Techniques, 2008, p. 72–81.
-
16)
-
Zhao, W., Belhaire, E., Mistral, Q.: `Macro-model of spin-transfer torque based magnetic tunnel junction device for hybrid magnetic- CMOS design', Proc. Int. Behavioral Modeling and Simulation Workshop, 2006, p. 40–43.
-
17)
-
P.S. Magnusson ,
M. Christensson ,
J. Eskilson
.
Simics: a full system simulation slatform.
Computer
,
2 ,
50 -
58
-
18)
-
C. Liu ,
I. Ganusov ,
M. Burtscher ,
S. Tiwari
.
Bridging the processor-memory performance gap with 3D IC technology.
IEEE Des. Test Comput.
,
6 ,
556 -
564
-
19)
-
Y. Xie ,
G.H. Loh ,
K. Bernstein
.
Design space exploration for 3D architectures.
J. Emerg. Technol. Comput. Syst.
,
2 ,
65 -
103
-
20)
-
NASA Advanced Supercomputing Division: NAS Parallel Benchmarks: available at: http://www.nas.nasa.gov/Resources/Software/npb.html.
-
21)
-
Thoziyoor, S., Muralimanohar, N., Ahn, J.-H., Jouppi, N.P.: `CACTI 5.1 Technical Report', Tech., 2008.
-
22)
-
Dong, X., Wu, X., Sun, G.: `Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement', Proc. Design Automation Conf., 2008, p. 554–559.
-
23)
-
Motoyoshi, M., Yamamura, I., Ohtsuka, W.: `A study for 0.18 µm high-density MRAM', Proc. Int. Symp. on VLSI Technology, 2004, p. 22–23.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt.2009.0091
Related content
content/journals/10.1049/iet-cdt.2009.0091
pub_keyword,iet_inspecKeyword,pub_concept
6
6