History-aware, resource-based dynamic scheduling for heterogeneous multi-core processors

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History-aware, resource-based dynamic scheduling for heterogeneous multi-core processors

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The authors introduce a history-aware, resource-based dynamic (or simply HARD) scheduler for heterogeneous chip multi-processors (CMPs). HARD relies on recording application resource utilisation and throughput to adaptively change cores for applications during runtime. The authors show that HARD can be configured to achieve both performance and power improvements and compare HARD to an alternative dynamic scheduler and a static scheduler to provide better understanding.

Inspec keywords: multiprocessing systems; processor scheduling; performance evaluation; microprocessor chips

Other keywords: HARD; heterogeneous multicore processors; history-aware resource-based dynamic scheduling; power improvements; application resource utilisation; heterogeneous chip multiprocessors; performance improvements; CMP

Subjects: Performance evaluation and testing; Microprocessor chips; Multiprocessing systems; Microprocessors and microcomputers

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