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Low-power hybrid complementary metal-oxide-semiconductor-nano-electro-mechanical systems field programmable gate array: circuit level analysis and defect-aware mapping

Low-power hybrid complementary metal-oxide-semiconductor-nano-electro-mechanical systems field programmable gate array: circuit level analysis and defect-aware mapping

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Conventional programmable fabric implemented in nanoscale complementary metal-oxide-semiconductor (CMOS) technologies suffer from large leakage power dissipation and volatility of the storage cells, which require reconfiguration at each power-on. In this study, the authors present a hybrid field programmable gate array design approach that can leverage on carbon nanotube (CNT)-based nano-electro-mechanical systems (NEMS) switches to implement memory elements leading to significant saving in static power dissipation. Besides, because of the non-volatile nature of the CNT-NEMS switches, the proposed framework eliminates the requirement of reconfiguration on start-up. To implement the programmable interconnects, the authors propose two alternative structures leveraging on non-volatile CNT-NEMS switches. To overcome the high defect density of a nano-fabric, the authors also propose a novel application mapping technique that can take advantage of certain defects modelled as stuck-at faults in the lookup tables (LUTs), thus considerably improving the yield. Simulations show that the proposed CMOS-NEMS LUT-based circuits can achieve an average reduction of 90% in leakage power at iso-performance, compared to the conventional CMOS-based LUT circuits. The proposed defect-aware mapping achieves an average improvement of 87% in the number of mapped functions over conventional mapping for 10% defect rate.

References

    1. 1)
    2. 2)
      • Orlowski, M.: `CMOS challenges of keeping up with Moore's Law', Proc. Int. Conf. Advanced Thermal Processing of Semiconductors, October 2005, p. 3–21
    3. 3)
      • Power, suddenly we care
    4. 4)
    5. 5)
      • Carbon nanotube-based nonvolatile random access memory for molecular computing
    6. 6)
    7. 7)
      • A three-terminal carbon nanorelay
    8. 8)
      • Jungen, A., Stampfer, C., Tonteling, M.: `Localized and CMOS compatible growth of carbon nanotubes on a 3×3 µm', Proc. TRANSDUCERS, June 2005, p. 93–96
    9. 9)
      • Hybridization of CMOS with CNT-based nano electromechanical switch for low leakage and robust circuit design
    10. 10)
      • Zhou, Y., Thekkel, S., Bhunia, S.: `Low power FPGA design using hybrid CMOS-NEMS approach', Proc. Int. Symp. Low Power Electronics and Design, August 2007, p. 14–19
    11. 11)
      • Mishra, M., Goldstein, S.C.: `Defect tolerance at the end of the roadmap', Proc. Int. Test Conf., September 2003, p. 1201–1210
    12. 12)
      • Buckling and collapse of embedded carbon nanotubes
    13. 13)
    14. 14)
    15. 15)
      • Quantum conductance of carbon nanotubes with defects
    16. 16)
      • Kolpekwar, A., Blanton, R.D., Woodilla, D.: `Failure mode for stiction in surface-micromachined MEMS', Proc. Int. Test Conf., October 1998, p. 551–556
    17. 17)
      • Naeimi, H., DeHon, A.: `Fault secure encoder and decoder for memory applications', Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems, September 2007, p. 409–417
    18. 18)
      • Goldstein, S.C., Budiu, M.: `Nano-fabrics: spatial computing using molecular electronics', Proc. Int. Symp. Comp. Arch., June 2001, p. 178–189
    19. 19)
      • Tehranipoor, M.: `Defect tolerance for molecular electronics-based nano-fabrics using built-in self-test procedure', Proc. Int. Conf. Defect and Fault-tolerance in VLSI Syst., October 2005, p. 305–313
    20. 20)
      • Brown, J.G., Blanton, R.D.: `CAEN-BIST: testing the nano-fabric', Proc. Int. Test Conf., October 2004, p. 462–471
    21. 21)
    22. 22)
      • Paul, S., Chakraborty, R.S., Bhunia, S.: `Defect-aware configurable computing in nanoscale crossbar for improved yield', Int. On-line Testing Symp., July 2007, p. 29–36
    23. 23)
      • The crossbar latch: logic value storage, restoration, and inversion in crossbar circuits
    24. 24)
      • Tahoori, M.B.: `A mapping algorithm for defect-tolerance of reconfigurable nano-architectures', Proc. Int. Conf. CAD, November 2005, p. 668–672
    25. 25)
      • Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies
    26. 26)
      • Srivastava, N., Banerjee, K.: `Performance analysis of carbon nanotube interconnects for VLSI applications', Proc. Int. Conf. CAD, November 2005, p. 383–390
    27. 27)
    28. 28)
      • http://www-device.eecs.berkeley.edu/~ptm/ (accessed December 2007)
    29. 29)
      • Lodi, A., Ciccarelli, L., Loparco, D.: `Low leakage design of LUT-based FPGAs', Proc. European Solid-State Circuits Conf., September 2005, p. 153–156
    30. 30)
      • A defect tolerant memory architecture for molecular electronics
    31. 31)
    32. 32)
      • Essentials of electronic testing for digital, memory & mixed signal vlsi circuits
    33. 33)
      • Digital system testing and testable design
    34. 34)
      • Tahoori, M.B.: `Defect & fault tolerance of reconfigurable molecular computing', Proc. Int. Symp. Field-programmable Custom Computing Machines, April 2004, p. 176–185
    35. 35)
      • Defect tolerance for nanoscale crossbar- based devices
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