Low-power hybrid complementary metal-oxide-semiconductor-nano-electro-mechanical systems field programmable gate array: circuit level analysis and defect-aware mapping

Low-power hybrid complementary metal-oxide-semiconductor-nano-electro-mechanical systems field programmable gate array: circuit level analysis and defect-aware mapping

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Conventional programmable fabric implemented in nanoscale complementary metal-oxide-semiconductor (CMOS) technologies suffer from large leakage power dissipation and volatility of the storage cells, which require reconfiguration at each power-on. In this study, the authors present a hybrid field programmable gate array design approach that can leverage on carbon nanotube (CNT)-based nano-electro-mechanical systems (NEMS) switches to implement memory elements leading to significant saving in static power dissipation. Besides, because of the non-volatile nature of the CNT-NEMS switches, the proposed framework eliminates the requirement of reconfiguration on start-up. To implement the programmable interconnects, the authors propose two alternative structures leveraging on non-volatile CNT-NEMS switches. To overcome the high defect density of a nano-fabric, the authors also propose a novel application mapping technique that can take advantage of certain defects modelled as stuck-at faults in the lookup tables (LUTs), thus considerably improving the yield. Simulations show that the proposed CMOS-NEMS LUT-based circuits can achieve an average reduction of 90% in leakage power at iso-performance, compared to the conventional CMOS-based LUT circuits. The proposed defect-aware mapping achieves an average improvement of 87% in the number of mapped functions over conventional mapping for 10% defect rate.


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