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Adaptive error control for nanometer scale network-on-chip links

Adaptive error control for nanometer scale network-on-chip links

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The authors present an adaptive error control method for switch-to-switch links in nanoscale networks-on-chip to manage reliability, throughput and energy. Unlike previous works, the proposed method adjusts both error detection and correction simultaneously at runtime. For a given application or predicted noise scenario, an appropriate error control scheme is selected for reliable message transmission. When link conditions degrade, more powerful error detection and correction are temporarily provided to recover the previous message. To achieve this adaptation, the authors create a configurable M-error correction, 2M-error detection code, combined with a hybrid automatic repeat request retransmission policy. Simulation results show that the proposed method can reduce residual flit error rate by over three orders of magnitude and achieve up to 75% higher average throughput compared to other error control methods. Further, average energy per successfully transmitted flit is reduced by up to 15% compared to fixed error control in a 65-nm technology. Compared to a recent adaptive error detection method, a 34% energy reduction can be achieved in high noise environment, at the expense of moderate area overhead.

References

    1. 1)
    2. 2)
    3. 3)
      • Salminen E., Kulmala A., Hämäläinen T.D.: ‘Survey of network-on-chip proposals’. White paper, OCP-IP, March 2008, p. 13.
    4. 4)
      • Dally, W.J., Towles, B.: `Route packets, not wires: on-chip interconnection networks', Proc. 38th Design Automation Conf. (DAC'01), June 2001, Las Vegas, NV, USA, p. 684–689.
    5. 5)
    6. 6)
      • T. Bjerregaard , S. Mahadevan . A survey of research and practices of network-on-chip. ACM Comput. Surv. , 1 , 1 - 51
    7. 7)
      • Dumitraş, T., Kerner, S., Mărculescu, R.: `Towards on-chip fault-tolerant communication', Proc. Asia and South Pacific Design Automation Conf., January 2003, Kitakyushu, Japan, p. 225–232.
    8. 8)
      • Mărculescu, R.: `Networks-on-chip: the quest for on-chip fault-tolerant communication', Proc. IEEE Computer Society Ann. Symp. VLSI (ISVLSI'03), February 2003, Tampa, FL, USA, p. 8–12.
    9. 9)
      • Bertozzi, D., Benini, L., Micheli, G.D.: `Low power error resilient encoding for on-chip data buses', Proc. Design, Automation, and Test in Europe (DATE'02), Le Palais des Congres, March 2002, Paris, France, p. 102–109.
    10. 10)
      • S. Murali , L. Benini , M.J. Irwin , G.D. Micheli . Analysis of error recovery schemes for networks on chips. IEEE Design Test Comput. , 5 , 434 - 442
    11. 11)
      • Ali, M., Welzl, M., Hessler, S., Hellebrand, S.: `A fault tolerant mechanism for handling permanent and transient failures in a network on chip', Proc. Intl. Technology: New Generations (ITNG'07), April 2007, Las Vegas, NV, USA, p. 1027–1032.
    12. 12)
    13. 13)
      • S. Komatsu , M. Fujita . Low power and fault tolerant encoding methods for on-chip data transfer in practical applications. IEICE Trans. Fundam. , 12 , 3282 - 3289
    14. 14)
    15. 15)
      • Ejlali, A., Al-Hashimi, B.M., Rosinger, P., Miremadi, S.G.: `Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks', Proc. Design, Automation, and Test in Europe (DATE'07), April 2007, Acropolis, Nice, France, p. 1647–1652.
    16. 16)
    17. 17)
      • Li, L., Vijaykrishnan, N., Kandemir, M., Irwin, M.J.: `Adaptive error protection for energy efficiency', Proc. Intl. Conf. Computer Aided Design (ICCAD'03), November 2003, San Jose, CA, USA, p. 2–7.
    18. 18)
      • A.K. Palit , K.K. Duganapallia , W. Anheiera . Crosstalk fault modeling in defective pair of interconnects. Integr. VLSI J. , 1 , 27 - 37
    19. 19)
      • A. Ganguly , P.P. Pande , B. Belzer , C. Grecu . Design of low power & reliable networks on chip through joint crosstalk avoidance and multiple error correction coding. J. Electron. Test. , 1 , 67 - 81
    20. 20)
      • G.D. Micheli , L. Benini . (2006) Networks on chips.
    21. 21)
      • Zimmer, H., Jantsch, A.: `A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip', Proc. Intl. Conf. Hardware/Software Codesign and Syst. Synthesis (CODES-ISSS'03), October 2003, Newport Beach, CA, USA, p. 188–193.
    22. 22)
      • Rossi, D., Angelini, P., Metra, C.: `Configurable error control scheme for NoC signal integrity', Proc. IEEE Intl. On-Line Testing Symp. (IOLTS 2007), Hersonissos-Heraklion, July 2007, Crete, Greece, p. 43–48.
    23. 23)
      • T. Lehtonen , P. Liljeberg , J. Plosila . Online reconfigurable self-timed links for fault tolerant NoC. VLSI Des.
    24. 24)
      • Yu, Q., Ampadu, P.: `Configurable error correction for multi-wire errors in switch-to-switch links', Proc. IEEE Intl. SOC Conf. (SOCC'08), September 2008, Newport Beach, CA, USA, p. 71–74.
    25. 25)
      • F. Worm , P. Ienne , P. Thiran , G.D. Micheli . A robust self-calibrating transmission scheme for on-chip network. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , 1 , 126 - 139
    26. 26)
      • Yu, Q., Ampadu, P.: `Adaptive error control for reliable systems-on-chip', Proc. Intl. Symp. Circuits and Syst. (ISCAS'08), May 2008, Seattle, WA, USA, p. 832–835.
    27. 27)
      • Yu, Q., Ampadu, P.: `Adaptive error control for NoC switch-to-switch links in a variable noise environment', Proc. 23rd IEEE Intl. Symp. Defect and Fault Tolerance in VLSI System (DFT'08), October 2008, Cambridge, MA, USA, p. 352–360.
    28. 28)
      • S. Lin , D.J. Costello . (2004) Error control coding.
    29. 29)
      • J.L. Nunez-Yanez , D. Edwards , A.M. Coppola . Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems. IET Comput. Dig. Tech. , 3 , 184 - 198
    30. 30)
      • M. Kousa , L. Turner . Reliability-throughput optimization for adaptive forward error correction systems. IEE Proc. Commun. , 6 , 341 - 346
    31. 31)
      • H. Minn , M. Zeng , V.K. Bhargava . On ARQ scheme with adaptive error control. IEEE Trans. Veh. Technol. , 6 , 1426 - 1436
    32. 32)
      • Fu, B., Ampadu, P.: `A dual-mode hybrid ARQ scheme for energy efficiency on-chip interconnects', Proc. 3rd Intl. Conf. Nano-Networks (Nano-Net'08), September 2008, Boston, MA, USA, p. 5.
    33. 33)
      • http://www.eas.asu.edu/~ptm/, accessed March 2009.
    34. 34)
      • D. Bertozzi , L. Benini . Xpipe: a network-on-chip architecture for gigascale systems-on-chip. IEEE Circuit Syst. Mag. , 18 - 31
    35. 35)
      • H.264/AVC JM Reference, http://iphome.hhi.de/suehring/tml/, accessed March 2009.
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