Inversion schemes for sublithographic programmable logic arrays

Inversion schemes for sublithographic programmable logic arrays

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A programmable logic array (PLA) needs its inputs available in both the positive and negative polarities. In lithographic-scale VLSI PLAs, programmable array logics (PALs) and programmable logic devices (PLDs) a buffer and inverter at the PLA input typically produces both polarities from a single polarity input. However, the extreme regularity required for sublithographic designs has driven nanoscale architectures to consider alternate solutions. Consequently, the authors compare three schemes: one based on producing both polarities in a restoration stage (selective inversion), one based on a local inversion stage and one based on a full dual-rail logic implementation. The authors develop a mapping flow for the dual-rail logic and quantify its cost in both logical product terms and physical implementation area and also develop area and timing models for all three schemes. Mapping benchmarks from the Toronto 20 set, the authors are able to show that the local inversion scheme is faster (less than one-fifth the latency), lower energy (one-half the energy) and comparable size to the selective inversion scheme and faster (less than half the latency), smaller (one-third of the area) and lower energy (one-ninth the energy) than the dual-rail scheme.


    1. 1)
      • Nanowire-based programmable architectures
    2. 2)
    3. 3)
      • Goldstein, S.C., Budiu, M.: `NanoFabrics: spatial computing using molecular electronics', Proc. Int. Symp. Computer Architecture, June 2001, p. 178–189
    4. 4)
      • A defect-tolerant computer architecture: opportunities for nanotechnology
    5. 5)
      • Two-dimensional molecular electronics circuits
    6. 6)
      • DeHon, A., Wilson, M.J.: `Nanowire-based sublithographic programmable logic arrays', Proc. Int. Symp. Field-Programmable Gate Arrays, February 2004, p. 123–132
    7. 7)
      • A laser ablation method for synthesis of crystalline semiconductor nanowires
    8. 8)
      • Diameter-controlled synthesis of single crystal silicon nanowires
    9. 9)
      • Germanium nanowire growth via simple vapor transport
    10. 10)
      • General syntehsis of manganese-doped II–VI and III–V semiconductor nanowires
    11. 11)
      • Ultrathin Au nanowires and their transport properties
    12. 12)
      • Controlled growth and structures of molecular-scale silicon nanowires
    13. 13)
      • Synthetic control of the diameter and length of semiconductor nanowires
    14. 14)
      • Preparation of gold, platinum, palladium and silver nanoparticles by the reduction of their salts with a weak reductant–potassium bitartrate
    15. 15)
    16. 16)
      • Epitaxial core–shell and core-multi-shell nanowire heterostructures
    17. 17)
      • Directed assembly of one-dimensional nanostructures into functional networks
    18. 18)
      • Nanolithography using hierarchically assembled nanowire masks
    19. 19)
      • Large-scale hierarchical organization of nanowire arrays for integrated nanosystems
    20. 20)
      • Nanoscale molecular-switch devices fabricated by imprint lithography
    21. 21)
    22. 22)
      • Si/a-si core/shell nanowires as nonvolatile crossbar switches
    23. 23)
      • Structures and electrical properties for ag-tetracyanoquinodimetheane organometallic nanowires
    24. 24)
      • High performance CMOS variability in the 65-nm regime and beyond
    25. 25)
    26. 26)
      • Introduction of catenanes into Langmuir films and Langmuir-Blodgett multilayers. a possible strategy for molecular information storage materials
    27. 27)
      • Seven strategies for tolerating highly defective fabrication
    28. 28)
      • ‘XC9500XV family high-performance CPLD data sheet’, Xilinx, Inc., San Jose, CA9, June 2002, v2.1 edn., dS049
    29. 29)
      • ‘MAX 7000 programmable logic device family data sheet’, (Altera Corporation, San Jose, CA, June 2003, v6.6 edn.,
    30. 30)
      • Agrawal, O.P.: `AMD's MACH family breaks PLD speed and density barrier', Proc. Annual IEEE ASIC Seminar and Exhibit, September 1990, p. P15/7.1–P15/7.4
    31. 31)
      • Ahrens, K., Khu, A.: `Innovations in the fifth generation MACH complex PLD family architecture', Conf. Record WESCON, November 1995, p. 196–199
    32. 32)
    33. 33)
    34. 34)
      • Kouloheris, J., El Gamal, A.: `PLA-based FPGA area versus cell granularity', Proc. IEEE Custom Integrated Circuits Conf. IEEE, May 1992, p. 4.3.1–4
    35. 35)
      • Kaviani, A., Brown, S.: `Hybrid FPGA architecture', Proc. Int. Symp. Field Programmable Gate Arrays, February 1996, p. 3–9
    36. 36)
    37. 37)
      • Performance-driven mapping for CPLD architectures
    38. 38)
      • Multiple-valued minimization for PLA optimization
    39. 39)
      • DeHon, A., Likharev, K.K.: `Hybrid CMOS/nanoelectronic digital circuits: Devices, architectures, and design automation', Proc. Int. Conf. Computer Aided Design, November 2005, p. 375–382
    40. 40)
      • Ultrahigh-density nanowire lattices and circuits
    41. 41)
    42. 42)
      • Goldstein, S.C., Rosewater, D.: `Digital logic using molecular electronics', ISSCC Digest of Technical Papers, February 2002, p. 204–205
    43. 43)
      • A programmable majority logic array using molecular scale electronics
    44. 44)
      • Rosewater, D.L., Goldstein, S.C.: `What makes a good molecular computing device?', Technical Report CMU-CS-02-181, Carnegie Mellon University, September 2002, [Online]. Available:
    45. 45)
      • Molecular electronics: from devices and interconnect to circuits and architecture
    46. 46)
      • Tsu, W., Macy, K., Joshi, A., Huang, R., Walker, N., Tung, T., Rowhani, O., George, V., Wawrzynek, J., DeHon, A.: `HSRA: high- speed, hierarchical synchronous reconfigurable array', Proc. Int. Symp. Field-Programmable Gate Arrays, February 1999, p. 125–134
    47. 47)
      • Leiserson, C., Rose, F., Saxe, J.: `Optimizing synchronous circuitry by retiming', Third Caltech Conf. On VLSI, March 1983
    48. 48)
      • Betz, V., Rose, J.: ‘FPGA Place-and-Route Challenge,’, 1999
    49. 49)
      • SIS: a system for sequential circuit synthesis
    50. 50)
      • Input variable assignment and output phase optimization
    51. 51)
      • Way, C.-L., Chang, T.-Y.: `PLAYGROUND: minimization of PLAs with mixed ground true outputs', Proc. ACM/IEEE Design Automation Conf., 1988, p. 421–426
    52. 52)
      • Betz, V., Rose, J.: `VPR: A new packing, placement, and routing tool for FPGA research', Proc. Int. Conf. Field-Programmable Logic and Applications, August 1997, Springer, p. 213–222, (LNCS, no. 1304
    53. 53)
      • Betz, V.: ‘VPR and T-VPack: versatile packing, placement and routing for FPGAs,’, March 27, 1999, version 4.30
    54. 54)
      • ‘International technology roadmap for semiconductors,’, 2003
    55. 55)
      • Single-crystal metallic nanowires and metal/semiconductor nanowire heterostructures
    56. 56)
      • Strukov, D.B., Likahrev, K.K.: `A reconfigurable architecture for hybrid CMOS/nanodevice circuits', Proc. Int. Symp. Field-Programmable Gate Arrays, 2006, p. 131–140

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