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Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies

Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies

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Published

Single event upsets (SEUs) and single event transients (SETs) are major reliability concerns in deep submicron technologies. As technology feature size shrinks, digital circuits are becoming more susceptible to SEUs and SETs. A novel SEU/SET-tolerant latch called feedback redundant SEU/SET-tolerant latch (FERST) is presented, where redundant feedback lines are used to mask SEUs and delay elements are used to filter SETs. Detailed SPICE simulations have been done to evaluate the proposed design and compare it with previous latch designs. The results show that the SEU tolerance of the FERST latch is almost equal to that of a TMR latch (a widely used latch which is the most reliable among the previous latches); however, the FERST latch consumes about 50% less energy and occupies 42% less area than the triple modular redundancy (TMR) latch. Furthermore, the results show that more than 90% of the injected SETs can be masked by the FERST latch if the delay size is properly selected.

Inspec keywords: flip-flops

Other keywords: triple modular redundancy latch; deep submicron technology; latch design; redundant feedback lines; single event upsets; digital circuits; low energy single event upset; SPICE simulation; single event transients; single event transient-tolerant latch

Subjects: Logic circuits; Logic and switching circuits

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