Analysis of shared-link AXI

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Analysis of shared-link AXI

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Published

Shared-link AXI provides decent communication performance and requires half the cost of its crossbar counterpart. The authors analysed the performance impact of the factors in a shared-link AXI system. The factors include interface buffer size, arbitration combination and task access setting (transfer mode mapping). A hybrid data locked transfer mode was also proposed to improve the performance due to AXI's extra transition cycle. The analysis is carried out by simulating a multi-core platform with a shared-link AXI backbone running a video phone application. The performance is evaluated in terms of bandwidth utilisation, average transaction latency and system task completion time. The analysis showed that channel-independent arbitration could contribute up to 23.2% of bandwidth utilisation and completion time difference. Moreover, the analysis suggests that the proposed hybrid data locked mode should be used only by long access latency devices. Such setting resulted in up to 21.1% completion time reduction compared with the setting without the hybrid data locked mode. The design options in shared-link AXI bus are also discussed.

Inspec keywords: multiprocessor interconnection networks; logic design; system buses; system-on-chip

Other keywords: multicore platform; channel-independent arbitration; system task completion time; video phone; interface buffer size; bandwidth utilisation; shared-link AXI bus; transfer mode mapping; hybrid data locked transfer mode; hybrid data locked mode

Subjects: Microprocessor chips; Digital circuit design, modelling and testing; Microprocessors and microcomputers; Logic design methods; System buses; Parallel architecture

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