Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

Efficient advanced encryption standard implementation using lookup and normal basis

Efficient advanced encryption standard implementation using lookup and normal basis

For access to this article, please select a purchase option:

Buy article PDF
$19.95
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Computers & Digital Techniques — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

A new type of advanced encryption standard (AES) implementation using a normal basis is presented. The method is based on a lookup technique that makes use of inversion and shift registers, which leads to a smaller size of lookup for the S-box than its corresponding implementations. The reduction in the lookup size is based on grouping sets of inverses into conjugate sets which in turn leads to a reduction in the number of lookup values. The above technique is implemented in a regular AES architecture using register files, which requires less interconnect and area and is suitable for security applications. The results of the implementation are competitive in throughput and area compared with the corresponding solutions in a polynomial basis.

References

    1. 1)
      • T. Al-Somani , A. Amin . Hardware implementations of GF(2̂m) arithmetic using normal basis. J. Appl. Sci. , 6 , 1362 - 1372
    2. 2)
      • Jing, M., Chen, Y., Chang, Y., Hsu, C.: `The design of a fast inverse module in AES', Proc. Info-tech and Info-net, Cong. ICII, 2001, p. 298–303.
    3. 3)
      • Hämäläinen, P., Alho, T., Hännikäinen, M., Hämäläinen, T.: `Design and implementation of low-area and low-power AES encryptionhardware core', Proc. 9th EUROMICRO Conf. Digital System Design (DSD′06), 2006, p. 577–583.
    4. 4)
      • Satoh, A., Morioka, S., Takano, K., Munetoh, S.: `A compact Rijndael hardware architecture with S-box optimization', Proc. Advances in Cryptology – ASIACRYPT 2001, 2001, p. 239–254.
    5. 5)
      • M. Feldhofer , J. Wolkerstorfer , V. Rijmen . AES implementation on a grain of sand. IEE Proc. Inf. Secur , 1 , 13 - 20
    6. 6)
      • M. McLoone , J. McCanny . Rijndael FPGA implementation utilizing look-up tables. J. VLSI Signal Process. Syst , 3 , 261 - 275
    7. 7)
      • Canright, D.: `A very compact S-box for AES', Proc. 7th Int. Workshop on Cryptographic Hardware and Embedded Systems (CHES 2005), 2005, p. 441–455, LCNS 3659.
    8. 8)
      • I. Verbauwhede , P. Schaumont , H. Kuo . Design and performance testing of a 2.29 GB/s Rijndael processor. IEEE J. Solid-State Circuits , 3 , 569 - 572
    9. 9)
      • Natl Inst. of Standards and Technology: ‘Federal Information Processing Standard 197, The Advanced Encryption Standard (AES)’, http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf,2001.
    10. 10)
      • Jeng, J.: `Normal basis inversion in some finite fields', 5thInt. Symp. Signal Processing and its Applications, ISSPA′99, August 1999, Brisbane, Australia, p. 701–703.
    11. 11)
      • A. Elbirt , W. Yip , B. Chetwynd , C. Paar . An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists. IEEE Trans. VLSI Syst. , 4 , 545 - 557
    12. 12)
      • N. Takagi , J. Yoshiki , K. Takagi . A fast algorithm for multiplicative inversion in GF(2∧m) using normal basis. IEEE Trans. Comp. , 5 , 394 - 398
    13. 13)
      • Huang, Y., Lin, Y., Hung, K., Lin, K.: `Efficient implementation of AES IP', Circuits and Systems 2006, APCCAS IEEE Conf., 2006, p. 1418–1421.
    14. 14)
      • D. Sokolov , J. Murphy , A. Bystrov , A. Yakovlev . Design and analysis of dual-rail circuits for security applications. IEEE Trans. Comp , 4 , 449 - 460
    15. 15)
      • Tillich, S., Feldhofer, M., Großschädl, J.: `Area, delay, and power characteristics of standard-cell implementations of the AES S-box', Proc. Embedded Computer Systems: Architectures, Modelling, and Simulation, July 2006, p. 457–466, LNCS 4017.
    16. 16)
      • Yu, N., Heys, H.: `Investigation of compact hardware implementation of the advanced encryption standard', Proc. IEEE Conf. CCECE, May 2005, Saskatoon, Saskatchewan, p. 1069–1072.
    17. 17)
      • Lin, T., Su, C., Huang, C., Wu, C.: `A high-throughput low-cost AES cipher chip', IEEE Proc. 3rd Asia-Pacific Conf. ASICS (AP-ASIC), August 2002.
    18. 18)
      • S. Mangard , M. Aigner , S. Dominikus . A highly regular and scalable AES hardware architecture. IEEE Trans. Comput. , 4 , 483 - 491
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt.2008.0049
Loading

Related content

content/journals/10.1049/iet-cdt.2008.0049
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address