New building block: multiplication-mode current conveyor

New building block: multiplication-mode current conveyor

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A new building block called the multiplication-mode current conveyor (MMCC) is proposed here. The structure consists of a differential voltage current conveyor (DVCC) and a folded Gilbert cell without any other auxiliary circuits. Based on the MMCC, a four-quadrant analogue multiplier is designed in TSMC 0.35 µm CMOS 2P4M processes with power supply ±1.65 V. HSPICE post-layout simulation results show that the maximum DC operating range is ±200 mV, the loading range is from 1 to 10 kΩ, the bandwidth is about 90 MHz, the total harmonic distortion (THD) is 0.85%, the power consumption is 1.08 mW and the chip area without pads is 0.48×0.36 mm2. The new square summer and analogue divider applications employing MMCCs are also presented.


    1. 1)
      • Analytical synthesis of current-mode high-order single-ended-input OTA and equal-capacitor elliptic filter structures with the minimum number of components
    2. 2)
      • Synthesis of leap-frog multiple-loop feedback OTA-C filters
    3. 3)
      • New current-mode all-pole and elliptic filters employing current conveyors
    4. 4)
      • A new CMOS electronically tunable current conveyor and its application to current-mode filters
    5. 5)
      • A novel floating lossy inductance realization topology with NICs using current conveyors
    6. 6)
      • A new pipelined analog-to-digital converter using current conveyors
    7. 7)
      • A novel hybrid active inductor
    8. 8)
      • CMOS differential difference current conveyors and their applications
    9. 9)
      • Analytical synthesis of low-sensitivity high-order voltage-mode DDCC and FDCCII-grounded R and C all-pass filter structures
    10. 10)
      • High-input and low-output impedance voltage-mode universal biquadratic filter using DDCCs
    11. 11)
      • Adaptive filter realization with a minimum number of multipliers
    12. 12)
      • A four-quadrant CMOS analog multiplier for analog neural networks
    13. 13)
      • Nonlinear circuit applications with current conveyors
    14. 14)
      • A CMOS multiplier/divider based on current conveyors
    15. 15)
      • Voltage-mode multiplier implementation employing current conveyors
    16. 16)
      • A 20-V four-quadrant CMOS analog multiplier
    17. 17)
      • A CMOS square-law vector summation circuit

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