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Concurrent error detection and correction in dual basis multiplier over GF(2m)

Concurrent error detection and correction in dual basis multiplier over GF(2m)

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Fault-based side-channel cryptanalysis is a useful technique against symmetrical and asymmetrical encryption/decryption algorithms. Thus, eliminating cryptographic computation errors become critical in preventing such kind of attacks. A simple way to eliminating cryptographic computation errors is to output correct or corrected ciphers. Multiplication is the most important finite field arithmetic operation in the cryptographic computations. By using time redundancy technique, a novel dual basis (DB) multiplier over Galois fields (2m) will be presented with lower space complexity and feedback-free property. Based on the proposed feedback-free DB multiplier, the DB multiplier with a concurrent error detection (CED) capability is also easily developed. Compared with the existing DB multiplier with CED capability, the proposed one saves about 90% of time-area complexity. No existing DB multiplier in the literature has concurrent error correction (CEC) capability. Based on the proposed DB multiplier, a novel DB multiplier with CEC capability is easily designed. The proposed DB multiplier with CEC capability requires only about 3% of extra space complexity and 15% of time complexity when compared with the proposed DB multiplier without CEC.

References

    1. 1)
      • The theory of error-correcting codes
    2. 2)
      • Introduction to finite fields and their applications
    3. 3)
      • Fast algorithms for digital signal processing
    4. 4)
      • The use of finite fields to compute convolutions
    5. 5)
      • Galois switching functions and their applications
    6. 6)
      • A VLSI design for computing exponentiation in GF(2m) and its application to generate pseudorandom number sequences
    7. 7)
      • Bit-serial Reed-Solomon encoder
    8. 8)
      • Efficient bit-serial multiplication and the discrete-time Wiener-Hopf equation over finite fields
    9. 9)
      • Computation with finite fields
    10. 10)
      • Mastrovito, E.D., Mora, T.: `VLSI architectures for multiplication over finite field GF(2', Proc. 6th Int. Conf., AAECC-6, July 1988, Rome, p. 297–309
    11. 11)
      • Mastrovito, E.D.: `VLSI architectures for computations in Galois fields', 1991, PhD, Linköping University, Department of Electrical Engineering, Linköping, Sweden, 1991
    12. 12)
      • Low-complexity bit-parallel canonical and normal basis multipliers for a class of finite fields
    13. 13)
      • Structure of parallel multipliers for a class of fields GF(2m)
    14. 14)
      • Modular construction of low complexity parallel multipliers for a class of finite fields GF(2m)
    15. 15)
      • Bit-parallel systolic multipliers for GF(2m) fields defined by all-one and equally-spaced polynomials
    16. 16)
      • Bit-parallel finite field multiplier and squarer using polynomial basis
    17. 17)
      • Efficient systolic arrays for power-sum, inversion, and division in GF(2m)
    18. 18)
      • Scalable and systolic architecture for computing double exponentiation over GF(2m)
    19. 19)
      • Low-complexity bit-parallel systolic architectures for computing A(x)B2(x) over GF(2m)
    20. 20)
      • Unified parallel systolic multipliers over GF(2m)
    21. 21)
      • Massey, J.L., Omura, J.K.: `Computational method and apparatus for finite field arithmetic', U.S., 4,587,627, 1986
    22. 22)
      • VLSI architectures for computing multiplications and inverses in GF(2m)
    23. 23)
      • A new construction of Massey-Omura parallel multiplier over GF(2m)
    24. 24)
      • Efficient normal basis multipliers in composite fields
    25. 25)
      • An efficient optimal normal basis type II multiplier
    26. 26)
      • A fast algorithm for multiplicative inversion in GF(2m) using normal basis
    27. 27)
      • Efficient design of low-complexity bit-parallel systolic Hankel multipliers to implement multiplication in normal and dual bases of GF(2m)
    28. 28)
      • Multiplexer-based double-exponentiation for normal basis of GF (2m)
    29. 29)
      • A comparison of VLSI architecture of finite field multipliers using dual, normal, or standard bases
    30. 30)
      • New low-complexity bit-parallel finite field multipliers using weakly dual bases
    31. 31)
      • Low complexity bit-parallel multipliers for a class of finite fields
    32. 32)
      • GF(2m) multiplication and division over the dual basis
    33. 33)
      • An algorithm to design finite field multipliers using a self-dual normal basis
    34. 34)
      • Dual basis systolic multipliers for GF(2m)
    35. 35)
      • Bit serial multiplication in finite fields
    36. 36)
      • New bit-serial systolic multiplier for GF(2m) using irreducible trinomials
    37. 37)
      • Boneh, D., DeMillo, R., Lipton, R.: `On the importance of checking cryptographic protocols for faults', Proc. Eurocrypt, 1999, p. 37–51, Springer LNCS 1233
    38. 38)
      • Biham, E., Shamir, A.: `Differential fault analysis of secret key cryptosystems', Proc. Crypto, 1997, p. 513–525, Springer LNCS 1294
    39. 39)
      • Kelsey, J., Schneier, B., Wagner, D., Hall, C.: `Side-channel cryptanalysis of product ciphers', Proc. ESORICS, September 1998, Springer, p. 97–110
    40. 40)
      • Anderson, R.J., Kuhn, M.: `Low cost attack on tamper resistant devices', Proc. 5th Int. Workshop on Security Protocols, 1997, Lecture Notes in Computer Sciences, Springer-Verlag, LNCS 1361
    41. 41)
      • Messerges, T.S., Dabbish, E.A., Sloan, R.H.: `Power analysis attacks on modular exponentiation in smartcards', Proc. Cryptographic Hardware and Embedded Systems (CHES'99), LNCS 1717, 1999
    42. 42)
      • Coron, J.S.: `Resistance against differential power analysis attacks for elliptic curve cryptosystems', Proc. Cryptographic Hardware and Embedded Systems (CHES'99), LNCS 1717, 1999, p. 292–302
    43. 43)
      • Karri, R., Kuznetsov, G., Goessel, M.: `Parity-based concurrent error detection of substitution-permutation network block ciphers', Proc. CHES 2003, 2003, Springer LNCS 2779, p. 113–124
    44. 44)
      • Error analysis and detection procedures for a hardware implementation of the advanced encryption standard
    45. 45)
      • Chinese remaindering based cryptosystems in the presence of faults
    46. 46)
      • On the importance of eliminating errors in cryptographic computations
    47. 47)
      • On-line error detection for bit-serial multipliers in GF(2m)
    48. 48)
      • Reyhani-Masoleh, A., Hasan, M.A.: `Error detection in polynomial basis multipliers over binary extension fields', Proc. Cryptographic Hardware and Embedded Systems-CHES 2002, LNCS 2523, 2003, p. 515–528
    49. 49)
      • Fault detection architectures for field multiplication using polynomial bases
    50. 50)
      • Concurrent error detection in a bit-parallel systolic multiplier for dual basis of GF(2m)
    51. 51)
      • Concurrent error detection in array multipliers for GF(2m) fields
    52. 52)
      • Concurrent error detection in a polynomial basis multiplier over GF(2m)
    53. 53)
      • Concurrent error detection in montgomery multiplication over GF(2m)
    54. 54)
      • Concurrent error detection in ALU's by recomputing with shifted operands
    55. 55)
      • Concurrent error detection in multiply and divide arrays
    56. 56)
      • Minero, R.H., Anello, A.J., Furey, R.G., Palounek, L.R.: `Checking by pseuduplication', U.S., 3660646, May 1972
    57. 57)
      • National Institute for Standards and Technology, ‘Digital Signature Standard’, FIPS publication 186-2, January 2000
    58. 58)
      • Hewlett Packard: ‘Table of low-weight binary irreducible polynomials’, HPL-98-135, 1998
    59. 59)
      • Principles of CMOS VLSI design: a system perspective
    60. 60)
      • M74HC86: ‘Quad exclusive OR gate, 2001 STMicroelectronics’, http://www.st.com/stonline/books/pdf/docs/2006.pdf
    61. 61)
      • M74HC08: ‘Quad 2-input AND gate, 2001 STMicroelectronics’, http://www.st.com/stonline/books/pdf/docs/1885.pdf
    62. 62)
      • M74HC174: ‘Hex D-type flip flop with clear, 2001 STMicroelectronics’, http://www.st.com/stonline/products/literature/ds/1914/M74HC174.pdf
    63. 63)
      • M74HC32: ‘Quad 2-input OR gate, 2001 STMicroelectronics’, http://www.st.com/stonline/books/pdf/docs/1944.pdf
    64. 64)
      • M74HC4075: ‘Triple 3-input OR gate, 2001 STMicroelectronics’, http://www.st.com/stonline/books/pdf/docs/1970.pdf
    65. 65)
      • Error detecting codes, self-checking circuits and applications
    66. 66)
      • VLSl architectures for computing exponentiations, multiplicative inverses, and divisions in GF(2m)
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