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Field programmable gate array-based design and realisation of automatic censored cell averaging constant false alarm rate detector based on ordered data variability

Field programmable gate array-based design and realisation of automatic censored cell averaging constant false alarm rate detector based on ordered data variability

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The design and field programmable gate array (FPGA)-based realisation of automatic censored cell averaging (ACCA) constant false alarm rate (CFAR) detector based on ordered data variability (ODV) is discussed here. The ACCA–ODV CFAR algorithm has been recently proposed in the literature for detecting radar target in non-homogeneous background environments. The ACCA–ODV detector estimates the unknown background level by dynamically selecting a suitable set of ranked cells and doing successive hypothesis tests. The proposed detector does not require any prior information about the background environment. It uses the variability index statistic as a shape parameter to accept or reject the ordered cells under investigation. Recent advances in FPGA technology and availability of sophisticated design tools have made it possible to realise the computation intensive ACCA–ODV detector in hardware, in a cost-effective way. The architecture is modular and has been implemented and tested on an Altera Stratix II FPGA using Quartus II software. The post place and route result show that the proposed design can operate at 100 MHz, the maximum clock frequency of the prototyping board and for this frequency the total processing time required to perform a single run is 0.21 µs. This amounts to a speedup for the FPGA-based hardware implementation by a factor of ∼110 as compared to software-based implementation, which takes 23 µs to perform the same operation.

References

    1. 1)
      • Radar system analysis and modeling
    2. 2)
      • Signal detection and estimation
    3. 3)
      • Reconfigurable computing: architectures and design methods
    4. 4)
      • Automatic censoring CFAR detector based on ordered data variability for nonhomogeneous environments
    5. 5)
      • Analysis of CFAR processors in nonhomogeneous background
    6. 6)
      • Cumplido, R., Torres, C., Lopez, S.: `A configurable FPGA-based hardware architecture for adaptive processing of noisy signals for target detection based on constant false alarm rate (CFAR) algorithms', Proc. Int. Signal Processing Conf. and Expo (GSPX'2004), September 2004, USA, CDROM
    7. 7)
      • Cumplido, R., Torres, C., Lopez, S.: `On the implementation of an efficient FPGA-based CFAR processor for target detection', Proc. 1st Int. Conf. Electrical and Electronics Engineering, June 2004, Acapulco, Mexico, p. 214–218
    8. 8)
      • El-Faramawy, N.M., El-Badawy, E.A., Salem, A.I.: `Hardware implementation of CA-CFAR processor', Proc. Int. Conf. Computer and Communication Engineering, May 2006, Kuala Lumpur, Malaysia, p. 573–578
    9. 9)
      • Design and implementation of a configurable real-time FPGA-based TM-CFAR processor for radar target detection
    10. 10)
      • Fahmy, S., Cheung, P., Luk, W.: `Novel FPGA-based implementation of median and weighted median filters for image processing', Proc. Int. Conf. Field Programmable Logic and Applications (FPL'2005), August 2005, p. 142–147
    11. 11)
      • Low cost sorting circuit for VLSI
    12. 12)
      • Quartus II user manual: http://www.altera.com/literature/lit-qts.jsp, accessed June 2008
    13. 13)
      • Stratix II development kit EP2S60 DSP user manual http://www.altera.com.cn/products/devkits/altera/kit-dsp-2S60.html, accessed June 2008
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