Field programmable gate array-based design and realisation of automatic censored cell averaging constant false alarm rate detector based on ordered data variability

Field programmable gate array-based design and realisation of automatic censored cell averaging constant false alarm rate detector based on ordered data variability

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The design and field programmable gate array (FPGA)-based realisation of automatic censored cell averaging (ACCA) constant false alarm rate (CFAR) detector based on ordered data variability (ODV) is discussed here. The ACCA–ODV CFAR algorithm has been recently proposed in the literature for detecting radar target in non-homogeneous background environments. The ACCA–ODV detector estimates the unknown background level by dynamically selecting a suitable set of ranked cells and doing successive hypothesis tests. The proposed detector does not require any prior information about the background environment. It uses the variability index statistic as a shape parameter to accept or reject the ordered cells under investigation. Recent advances in FPGA technology and availability of sophisticated design tools have made it possible to realise the computation intensive ACCA–ODV detector in hardware, in a cost-effective way. The architecture is modular and has been implemented and tested on an Altera Stratix II FPGA using Quartus II software. The post place and route result show that the proposed design can operate at 100 MHz, the maximum clock frequency of the prototyping board and for this frequency the total processing time required to perform a single run is 0.21 µs. This amounts to a speedup for the FPGA-based hardware implementation by a factor of ∼110 as compared to software-based implementation, which takes 23 µs to perform the same operation.


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