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Efficient driving-capability programmable frequency divider with a wide division ratio range

Efficient driving-capability programmable frequency divider with a wide division ratio range

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A programmable frequency divider with close-to-50% output duty-cycle, with a wide division ratio range, is presented. The proposed divider has also provisions for binary division ratio controls, and has demonstrated operation at frequencies as high as 3.5 GHz. With the above features, the proposed divider can be used in phase-locked loops, and is capable of driving various clocked circuits, which need different clock frequencies. The proposed divider has division ratios from 8 to 510, but it can easily be extended to higher ranges by simply adding more divider stages. The divider circuit has been realised in a 0.18-μm RF CMOS process. Test results show that the output duty-cycle is 50% when the division ratio is an even number. For odd division ratios the worst-case duty-cycle is 44.4% when the division ratio is 9. The output duty-cycle becomes closer to 50% when the division ratio is an increasing odd number. For each division ratio, the output duty-cycle remains constant for different chips, with different input frequencies from gigahertz down to kilohertz ranges, and with different power supply voltages.

Inspec keywords: CMOS integrated circuits; MMIC; programmable circuits; frequency dividers; phase locked loops

Other keywords: clocked circuits; programmable frequency divider; phase-locked loops; output duty-cycle; binary division ratio controls; RF CMOS process

Subjects: Convertors; Modulators, demodulators, discriminators and mixers; CMOS integrated circuits; Microwave integrated circuits

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