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Efficient driving-capability programmable frequency divider with a wide division ratio range

Efficient driving-capability programmable frequency divider with a wide division ratio range

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A programmable frequency divider with close-to-50% output duty-cycle, with a wide division ratio range, is presented. The proposed divider has also provisions for binary division ratio controls, and has demonstrated operation at frequencies as high as 3.5 GHz. With the above features, the proposed divider can be used in phase-locked loops, and is capable of driving various clocked circuits, which need different clock frequencies. The proposed divider has division ratios from 8 to 510, but it can easily be extended to higher ranges by simply adding more divider stages. The divider circuit has been realised in a 0.18-μm RF CMOS process. Test results show that the output duty-cycle is 50% when the division ratio is an even number. For odd division ratios the worst-case duty-cycle is 44.4% when the division ratio is 9. The output duty-cycle becomes closer to 50% when the division ratio is an increasing odd number. For each division ratio, the output duty-cycle remains constant for different chips, with different input frequencies from gigahertz down to kilohertz ranges, and with different power supply voltages.

References

    1. 1)
      • R.E. Best . (2003) Phase-locked loops design, simulation, and applications.
    2. 2)
    3. 3)
    4. 4)
    5. 5)
      • Khadanga, S.: `Synchronous programmable divider design for PLL using 0.18 µm CMOS technology', Proc. 3rd IEEE Int. Workshop on System-on-Chip for Real-Time Applications, 2003, p. 281–286.
    6. 6)
      • Guermandi, D., Franchi, E., Gnudi, A., Baccarani, G.: `A CMOS programmable divider for RF multistandard frequency synthesizers', Proc. 28th European Solid-State Circuits Conf., 2002, p. 843–846.
    7. 7)
    8. 8)
    9. 9)
      • http://www.nodna.com/fileadmin/download/INEX/Robo-51/AT89 C51AC2manual.pdf accessed August 2007.
    10. 10)
      • http://datasheets.maxim-ic.com/en/ds/MXB7843.pdf, accessed August 2007.
    11. 11)
    12. 12)
    13. 13)
      • Yang, W.B., Kuo, S.C., Chu, Y.H., Cheng, K.H.: `The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50% duty cycle', Proc. 2005 European Conf. Circuit Theory and Design, 2005, 3, p. III/193–III/196.
    14. 14)
      • Wang, Y.M., Wang, J.S.: `An all-digital 50% duty-cycle corrector', Proc. Int. Symp. Circuits and Systems, May 2004, 2, p. II - 925–928.
    15. 15)
      • Bui, H.T., Savaria, Y.: `High speed differential pulse-width control loop based on frequency-to-voltage converters', GLSVLSI'06, April 30–May 2 2006, p. 53–56.
    16. 16)
      • Li, L., Chen, J.H., Chang, R.C.: `A low jitter delay-locked loop with a realignment duty cycle corrector', Proc. IEEE Int. SOC. Conf., September 2005, p. 73–76.
    17. 17)
      • T. Gawa , K. Taniguchi . A 50% duty-cycle correction circuit for PLL output. IEEE Int. Symp. Circuits Syst. , IV - 21
    18. 18)
      • Wang, H.M.: `A 1.8 V 3 mW 16.8 GHz frequency divider in 0.25 µm CMOS', IEEE Int. Solid-State Circuits Conf., Digest of Technical Papers, February 2000, p. 196–197.
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