Low-power high‐speed performance of current-mode logic D flip-flop topology using negative-differential-resistance devices

T. Kim; Y. Jeong; K. Yang

Low-power high‐speed performance of current-mode logic D flip-flop topology using negative-differential-resistance devices

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Low-power high‐speed performance of current-mode logic D flip-flop topology using negative-differential-resistance devices

Author(s): T. Kim ; Y. Jeong ; K. Yang
DOI: 10.1049/iet-cds:20070135

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Author(s): T. Kim ¹ ; Y. Jeong ¹ ; K. Yang ¹
- Affiliations: 1: Division of Electrical Engineering, Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Republic of Korea
Source: Volume 2, Issue 2, April 2008, p. 281 – 287
DOI: 10.1049/iet-cds:20070135 , Print ISSN 1751-858X, Online ISSN 1751-8598

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The low-power/high-speed performance of current-mode logic (CML) D flip-flops based on negative-differential-resistance (NDR) devices is presented. The device count used in the fabricated circuit has been significantly reduced by using the NDR-based D flip-flop topology, leading to enhanced low-power/high-speed performance. The operation of the fabricated NDR-based CML D flip-flop has been confirmed to 36 Gb/s, which is the highest speed among NDR-based differential‐mode D flip-flops reported to date. The power consumption of the D flip-flop core circuit was measured to be as low as 20 mW at a power supply voltage of −3.3 V. In addition, a power–delay product of 0.55 pJ has been obtained from the NDR-based CML D flip-flop, which is the lowest value to the authors' knowledge among the previously reported D flip-flops up to operation speeds in the region of 40 Gb/s.

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Low-power high‐speed performance of current-mode logic D flip-flop topology using negative-differential-resistance devices

Low-power high‐speed performance of current-mode logic D flip-flop topology using negative-differential-resistance devices

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