Scaling considerations for sub-90 nm split-gate flash memory cells
A systematic methodology is presented to scale split-gate (SG) flash memory cells in the sub-90 nm regime within the presently known scaling constraints of flash memory. The numerical device simulation results show that the high performance sub-90 nm NOR-type SG cells can be achieved by a suitable channel and source–drain engineering. An asymmetric channel doping profile along with ultra-shallow source–drain junctions was used to achieve the target drain programming voltage (Vsp) for an efficient cell programming while keeping the cell breakdown voltage, BV>Vsp, with tolerable leakage currents. The study shows that with properly optimised technology parameters, 65 nm SG-NOR flash memory can be achieved with an adequate cell read current, a tolerable programmed cell leakage current at the read condition and efficient write and erase times.
