http://iet.metastore.ingenta.com
1887

Temperature dependence of IDDQ distribution: application for thermal delta IDDQ testing

Temperature dependence of IDDQ distribution: application for thermal delta IDDQ testing

For access to this article, please select a purchase option:

Buy article PDF
$19.95
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Circuits, Devices & Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

The increase in process parameter variations and off-state current for deep submicron complementary metal oxide semiconductor (CMOS) technologies makes conventional (single threshold) IDDQ testing ineffective. Delta IDDQ testing performed at two temperatures for a given test vector and called ‘thermal delta IDDQ testing’ is a more attractive alternative and is investigated by the authors. On the basis of statistical Monte Carlo simulations and industrial data, it is shown that lowering the temperature from 330 K to 280 K results in a more than ×100 reduction of IDDQ mean value and approximately ×15 reduction of IDDQ standard deviation of defect-free 0.18 µm CMOS circuits.

References

    1. 1)
    2. 2)
      • Kruseman, B.: `Comparison of defect detection capabilities of current-based and voltage-based test methods', Proc. ETW, 2000, p. 175–180.
    3. 3)
      • Kruseman, B., van Veen, R., van Kaam, K.: `The future of delta I', Proc. ITC, 2001, p. 101–110.
    4. 4)
      • Sachdev, M.: `Deep submicron I', Proc. European Design and Test Conf., 1997, p. 271–278.
    5. 5)
      • Keshavarzi, A., Narendra, S., Borkar, S., Hawkins, C., Roy, K., De, V.: `Technology scaling behavior of optimum reverse body bias for stand-by leakage power reduction in CMOS IC's', Proc. ISLPED, 1999, p. 252–254.
    6. 6)
      • Mistry, M., Ghani, T., Armstrong, M., Tyagi, S., Packan, P., Thompson, S., Yu, S., Bohr, M.: `Scalability revisited: 100 nm PD-SOI transistors and implications for 50 nm devices', Proc. Symp. VLSI Technol, 2000, p. 204–205.
    7. 7)
    8. 8)
      • Keshavarzi, A., Ma, S., Narendra, S., Bloechel, B., Mistry, K., Ghani, T., Borkar, S., De, V.: `Effectiveness of reverse body bias for leakage control in scaled dual V', Proc. ISLPED, 2001, p. 207–212.
    9. 9)
      • De, V., Narendra, S., Antoniadis, D.: `Impact of using adaptive body bias to compensate die-to-die V', Proc. ISLPED, 1999, p. 229–232.
    10. 10)
      • Gattiker, A., Maly, W.: `Current signatures: applications', Proc. IEEE Int. Test Conf. (ITC'97), 1997, p. 156–165.
    11. 11)
      • Thibeault, C.: `An histogram based procedure for current testing of active defects', Proc. IEEE Int. Test Conf. (ITC'99), 1999, p. 714–723.
    12. 12)
      • Sachdev, M., Janssen, P., Zieren, V.: `Defect detection with transient current testing and its potential for deep submicron ICs', Proc. IEEE Int. Test Conf. (ITC'98), 1998, p. 204–213.
    13. 13)
      • Miller, A.C.: `I', Proc. IEEE Int. Test Conf. (ITC'99), 1999, p. 724–729.
    14. 14)
    15. 15)
      • A. Singh , J. Plusquellic , D. Phatak , C. Patel . Defect simulation methodology for iDDT testing. J. Electron. Test., Theory Appl. , 255 - 272
    16. 16)
      • van Lammeren, J.P.M.: `ICCQ: a test method for analogue VLSI based on current monitoring', Proc. IEEE Int. Workshop on IDDQ Testing (IDDQ'97), 1997, p. 24–28.
    17. 17)
      • Maxwell, P., O'Neill, P., Aitken, R., Dudley, R., Jaarsma, N., Quach, M., Wiseman, D.: `Current ratios: a self-scaling technique for production I', Proc. ITC, 1999, p. 738–737.
    18. 18)
      • Lakin, D.R., Singh, A.D.: `Exploiting defect clustering to screen bare die for infant mortality failures: an experimental study', Proc. ITC, 1999, p. 23–30.
    19. 19)
    20. 20)
      • S.S. Sabade , D.M. Walker . IC outlier identification using multiple test metrics. IEEE Des. Test Comput. , 6 , 586 - 595
    21. 21)
      • J. Plusquellic , D. Acharyya , A. Singh , M. Tehranipoor , C. Patel . Quiescent-signal analysis: a multiple supply pad IDDQ method. IEEE Des. Test Comput. , 4 , 278 - 293
    22. 22)
      • Kundu, S., Engelke, P., Polian, I., Becker, B.: `On detection of resistive bridging defects by low-temperature and low-voltage testing', 14thAsian Test Symp. (ATS'05), 2005, p. 266–271.
    23. 23)
      • Engelke, P., Polian, I., Manhaeve, H., Renovell, M., Becker, B.: `Delta-I', Proc. Asian Test Symp., 2006, p. 63–68.
    24. 24)
      • Williams, T.W., Dennard, R.H., Kapur, R., Mercer, M.R., Malu, M.: `I', Proc. ITC, 1996, p. 786–792.
    25. 25)
      • V. Szekely , M. Rencz , S. Torok , B. Courtois . Cooling as a possible way to extend the usability of IDDQ testing. Electron. Lett. , 25 , 2117 - 2118
    26. 26)
      • M. Rencz , V. Szekely , S. Torok , K. Turki , B. Courtois . IDDQ testing of submicron CMOS—by cooling?. J. Electron. Test., Theory Appl. , 453 - 461
    27. 27)
    28. 28)
      • Shimaya, M.: `New screening concept for deep submicron CMOS VLSIs using temperature characteristics of leakage currents in MOS devices', Proc. IRPS, 1997, p. 49–56.
    29. 29)
      • Miyake, T., Yamashita, T., Asari, N., Sekisaka, H., Sakai, T., Matsuura, K., Wakahara, A., Takahashi, H., Hiyama, T., Miyamoto, K., Mori, K.: `Design methodology of high performance microprocessor using ultra-low threshold voltage CMOS', IEEE Conf. on Custom Integrated Circuits, 2001, San Diego, CA, USA, p. 275–278.
    30. 30)
      • Fukuda, T., Honzawa, A., Wada, S., Mori, K., Kunitomo, H., Sato, H.: `A statistical design methodology of a 0.12 μm CMOS device', Proc. Int. Workshop on Statistical Methodology, 2001, p. 54–57.
    31. 31)
      • Hawkins, C., Keshavarzi, A., Segura, J.: `A view from the bottom: nanometer technology AC parametric failures—why, where, and how to detect', Proc. DFT, 2003, p. 267–276.
    32. 32)
    33. 33)
      • Fukuma, M.: `New frontiers of sub-100 nm VLSI technology—Moving toward device and circuits co-design', Proc. IEEE Symp. on VLSI Technology, 2000, p. 4–7.
    34. 34)
      • N. Arora . (1993) MOSFET models for VLSI circuit simulations: theory and practice.
    35. 35)
    36. 36)
      • Lisenker, B., Mitnick, Y.: `Fault model for VLSI circuits reliability assessment', Proc. IRPS, 1999, p. 319–326.
    37. 37)
      • Variyam, P.N.: `Increasing the I', Proc. ITC, 2000, p. 217–224.
    38. 38)
      • Zeitzoff, P.M., Tasch, A.F., Moore, W.E., Khan, S.A., Angelo, D.: `Modeling of manufacturing sensitivity and statistically based process control requirements for a 0.18 μm NMOS device', Proc. Int. Conf. on Modeling of Manufacturing Sensitivity, 1998, p. 73–81.
    39. 39)
      • Miyama, M., Kamohara, S., Okuyama, K., Oji, Y.: `Parametric yield enhancement system via circuit level device optimization using statistical circuit simulations', Proc. Symp. on VLSI Circuits, 2001, p. 163–166.
    40. 40)
      • SEQUOIA Device Designer User's Guide, Sequoia Design Systemshttp://www.sequoiadesignsystems.com.
    41. 41)
    42. 42)
      • Powell, T.J., Pair, J., St. John, M.: `Delta I', Proc. 8th IEEE VLSI Test Symp., Montreal, Quebec, Canada, p. 439–443.
    43. 43)
      • Kalb, J.: `Method for testing a semiconductor device by measuring quiescent currents (I', US Patent #5,742,177, 1998.
    44. 44)
      • O. Semenov , A. Vassighi , M. Sachdev . Leakage current in sub-quarter micron MOSFET: a perspective on stressed delta IDDQ testing. J. Electron. Test., Theory Appl. , 3 , 341 - 352
    45. 45)
      • Kruseman, B., van gen Oetelaar, S.: `Detection of resistive shorts in deep submicron technologies', Proc. ITC, 2003, p. 866–875.
    46. 46)
      • S. Kundu . IDDQ defect detection in deep submicron CMOS ICs. Asian Test Symp. , 150 - 152
    47. 47)
      • Q-Star Test Companyhttp://www.qstar.be/html/bicmon.html.
    48. 48)
      • Hawkins, C., Keshavarzi, A., Segura, J.: `Parametric timing failure and defect-based testing in nanotechnology CMOS digital ICs', 11thNASA Symp. on VLSI Design, May 2003.
    49. 49)
      • A. Keshavarzi , K. Roy , C.F. Hawkins , V. De . Multi-parameter CMOS IC testing with increased sensitivity for IDDQ. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , 5 , 863 - 870
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds_20070074
Loading

Related content

content/journals/10.1049/iet-cds_20070074
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address