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Design of a rugged 60 V VDMOS transistor

Design of a rugged 60 V VDMOS transistor

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Vertical double diffused MOSFET (VDMOS) is an established technology for high-current power-switching applications such as automotive circuits. The most serious failure mode is destructive damage during inductive switching, resulting from avalanche breakdown of the forward-blocking junction in the presence of high current flow. Improving the ruggedness of the device is achieved by enhancing its ability to absorb inductive energy under avalanche conditions. The purpose of the paper is to explore the possibility of improving the ruggedness of VDMOS through TCAD simulations. A p+-strip buried underneath an n+-source is proposed to suppress the turn-on of the parasitic bipolar transistor. VDMOS transistors with this design modification are expected to have higher ruggedness while maintaining its superior figure-of-merit.

References

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    3. 3)
      • Kinzer, D., Ajit, J.S., Wagers, K., Asselanis, D.: `A high density self-aligned 4-mask planar VDMOS process', Proc. Power Semiconductor Devices and ICs, 1996, Hawaii, USA, p. 243–247.
    4. 4)
      • Murray, A., Davis, H., Cao, J., Spring, K., McDonald, T.: `New power MOSFET technology with extreme ruggedness and ultra-low RDS(on) qualified to Q101 for automotive applications', PCIM2000, Europe, p. 102–107.
    5. 5)
      • Philips Semiconductor Applications AN10273_1: ‘Power MOSFET single-shot and repetitive avalanche ruggedness rating’. Philips Semiconductors, 2003.
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