RT Journal Article
A1 E. Napoli

PB iet
T1 Limits and application of the newly proposed deep-depletion SOI LDMOS
JN IET Circuits, Devices & Systems
VO 1
IS 5
SP 366
OP 371
AB The behaviour of a deep depletion (DD) silicon on insulator (SOI) lateral MOS (LDMOS) is analysed. DD of the substrate for an SOI device has been recently proposed as an innovative technique to design power devices featuring a transient breakdown higher than the static breakdown. DD is a dynamic effect that allows the design of a whole new generation of SOI power devices. Eligible applications are power conditioning circuits in which the device sustains transient voltages higher than bus voltage such as the flyback converter and the resonant circuits. Numerical simulation methods are used to analyse the behaviour of the device together with the effect of temperature, substrate carrier generation time and applied reverse bias on the duration of the transient breakdown phase. The results show that the newly proposed DD SOI device, an SOI power LDMOS using P− substrate, exhibits a static breakdown voltage of 190 V and sustains transient overvoltages up to 280 V. Furthermore, mixed-mode simulation of a complete Class E resonant converter using the proposed DD SOI device is presented.
K1 mixed mode simulation
K1 flyback converter
K1 resonant converter
K1 bus voltage
K1 static breakdown voltage
K1 DD SOI device
K1 power conditioning circuits
K1 transient breakdown phase
K1 resonant circuits
K1 transient voltages
K1 voltage 190 V
K1 carrier generation time
K1 LDMOS
K1 lateral MOS
K1 complete Class E
K1 applied reverse bias
K1 deep depletion
DO https://doi.org/10.1049/iet-cds:20070004
UL https://digital-library.theiet.org/;jsessionid=152vab2zxdxic.x-iet-live-01content/journals/10.1049/iet-cds_20070004
LA English
SN 1751-858X
YR 2007
OL EN