http://iet.metastore.ingenta.com
1887

Limits and application of the newly proposed deep-depletion SOI LDMOS

Limits and application of the newly proposed deep-depletion SOI LDMOS

For access to this article, please select a purchase option:

Buy article PDF
$19.95
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Circuits, Devices & Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

The behaviour of a deep depletion (DD) silicon on insulator (SOI) lateral MOS (LDMOS) is analysed. DD of the substrate for an SOI device has been recently proposed as an innovative technique to design power devices featuring a transient breakdown higher than the static breakdown. DD is a dynamic effect that allows the design of a whole new generation of SOI power devices. Eligible applications are power conditioning circuits in which the device sustains transient voltages higher than bus voltage such as the flyback converter and the resonant circuits. Numerical simulation methods are used to analyse the behaviour of the device together with the effect of temperature, substrate carrier generation time and applied reverse bias on the duration of the transient breakdown phase. The results show that the newly proposed DD SOI device, an SOI power LDMOS using P substrate, exhibits a static breakdown voltage of 190 V and sustains transient overvoltages up to 280 V. Furthermore, mixed-mode simulation of a complete Class E resonant converter using the proposed DD SOI device is presented.

References

    1. 1)
      • B. Murari , F. Bertotti , G.A. Vignola . (2002) Smart power ICs.
    2. 2)
    3. 3)
      • Merchant, S., Arnold, E., Baumgart, H., Mukherjee, S., Pein, H., Pinker, R.: `Realization of high breakdown voltage (>700 V) in thin SOI devices', Proc. Int. Symp. Power Semiconductor Devices and ICs, April 1991, Baltimore, MD, p. 31–35.
    4. 4)
      • Merchant, S., Arnold, E., Baumgart, H., Mukherjee, S., Pein, H., Pinker, R.: `High breakdown voltage devices in ultra thin SOI', Proc. Int. Silicon on Insulator Conf., October 1991, p. 150–151.
    5. 5)
      • Merchant, S., Arnold, E., Simpson, M.: `Tunneling in thin SOI high voltage devices', Proc. Int. Symp. Power Semiconductor Devices and ICs, May 1995, Yokohama, Japan, p. 130–135.
    6. 6)
      • Jeon, B.C., Kim, D.Y., Lee, Y.S., Oh, J.K., Han, M.K., Choi, Y.I.: `Buried air gap structure for improving the breakdown voltage of SOI power MOSFET's', Proc. Electron. Motion Control Conf., August 2000, Beijing, China, p. 3.1061–3.1063.
    7. 7)
      • I.J. Kim , S. MatSumoto , T. Sakai . Breakdown voltage improvement for thin-film SOI power MOSFET's by a buried oxide step structure. IEEE Electron Device Lett. , 5 , 148 - 150
    8. 8)
      • Udrea, F., Trajkovic, T., Amaratunga, G.A.J.: `Membrane high voltage devices – a milestone concept in power ICs', IEEE Electron Devices Meeting, December 2004, San Francisco, CA, p. 451–454.
    9. 9)
      • Udrea, F., Trajkovic, T., Lee, C.: `Ultra-fast LIGBT2 and superjunction devices in membrane technology', Proc. Int. Symp. Power Semiconductor Devices and ICs, May 2005, Santa Barbara, CA, p. 267–270.
    10. 10)
      • Napoli, E., Udrea, F.: `Circuital implementation of deep depletion SOI power devices', Proc. Symp. Power Electronics, Electrical Drives, Automation and Motion, May 2006, Taormina, Italy, p. S38.9–S38.13.
    11. 11)
      • Napoli, E., Udrea, F.: `Substrate deep depletion: an innovative design concept to improve the voltage rating of SOI power devices', Proc. Int. Symp. Power Semiconductor Devices and ICs, June 2006, Napoli, Italy, p. 57–60.
    12. 12)
      • Napoli, E., Udrea, F.: `Physics, limits and application of the newly proposed deep depletion SOI power devices', Int. Seminar on Power Semiconductors, August 2006, Prague, p. 165–169, Czech Republic.
    13. 13)
    14. 14)
      • Napoli, E.: `Deep depletion SOI power devices', Proc. Int. Semiconductor Conf., September 2006, Sinaia, Romania, p. 3–12.
    15. 15)
      • A.S. Grove . (1967) Physics and technology of semiconductor devices.
    16. 16)
      • F.P. Heiman . Thin-film silicon on sapphire deep depletion MOS transistors. IEEE Trans. Electron Devices , 12 , 855 - 862
    17. 17)
      • S.R. Hofstein . An analysis of deep depletion thin-film MOS transistors. IEEE Trans. Electron Devices , 12 , 846 - 855
    18. 18)
      • Nakagawa, A., Nakamura, K., Yamaguchi, Y.: `Design optimization of 500V 1A SOI 1 chip inverter ICs', Proc. Power Electronics Conf., March 2003, Shanghai, China, p. 94–98.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds_20070004
Loading

Related content

content/journals/10.1049/iet-cds_20070004
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address