Characterisation of P floating islands for 150–200 V FLYMOSFETs

Characterisation of P floating islands for 150–200 V FLYMOSFETs

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A vertical N-channel 150–200 V FLYMOSFET concept has been applied on silicon: its P-buried layer introduced in the N epitaxial region, called ‘P floating island’, is the key factor for superior performance. A particular physical characterisation technique, scanning capacitance microscopy, is used on a power device to establish 2D and 3D island representation and to go beyond 1D information given by spreading resistance profiling. Experiments including four different boron implantations of P floating islands and two different spacings of the basic cell are conducted, because the form and the concentration of the floating islands and, moreover, the spacing between them directly impact the electrical performance. Concerning the electrical study, FLYMOSFET measurements show good ‘specific on-resistance/breakdown voltage’ (RON.S–BVdss) trade-offs, better than the conventional VDMOSFETs, and UIS ruggedness as good as superjunction MOSFETs.


    1. 1)
      • B.J. Baliga . (1987) Modern power devices,.
    2. 2)
      • T. Fujihira . Theory of semiconductor superjunction devices. Jpn. J. Appl. Phys. , 6254 - 6262
    3. 3)
      • Alves, S., Morancho, F., Reynès, J.-M., Lopes, B.: `Vertical N-channel FLIMOSFET for future 12 V/42 V dual batteries automotive applications', Proc. ISPSD'2003, 2003, Cambridge, p. 308–311.
    4. 4)
      • Alves, S., Morancho, F., Reynès, J.-M., Margheritta, J., Deram, I., Isoird, K.: `Experimental validation of the “FLoating Island” concept: a 95 Volts vertical breakdown voltage FLIDiode', Proc. ISPS'04, 2004, Prague, p. 47–50.
    5. 5)
      • W. Saito , I. Omura , K. Tokano , T. Ogura , H. Ohashi . A novel low on-resistance Schottky-barrier diode with p-buried floating layer structure. IEEE Trans. Electron Devices , 5 , 797 - 802
    6. 6)
      • X.B. Chen , X. Wang , J.K.O. Sin . A novel high-voltage sustaining structure with buried oppositely doped regions. IEEE Trans. Electron Devices , 6 , 1280 - 1285
    7. 7)
      • Cézac, N., Morancho, F., Rossel, P., Tranduc, H., Peyre-Lavigne, A.: `A new generation of power unipolar devices: the concept of the floating islands MOS transistor (FLIMOST)', Proc. ISPSD'2000, Toulouse, 2000, p. 69–72.
    8. 8)
      • K. Fischer , K. Shenai . Dynamics of power MOSFET switching under unclamped inductive loading conditions. IEEE Trans. Electron Devices , 1007 - 1015
    9. 9)
      • Digital Instruments Veeco Metrology.: ‘Scanning capacitance microscopy (SCM)’. Support Note No. 289, Rev. A, 2000, pp. 1–52.
    10. 10)
      • S.C. Choo , M.S. Leong , J.H. Sim . An efficient numerical scheme for spreading resistance calculations based on the variation method. Solid State Electron. , 8 , 723 - 730
    11. 11)
      • Saito, W., Omura, I., Aida, S., Koduki, S.: `A 20 mΩ.cm', Proc. ISPSD'2004, 2004, p. 459–462.
    12. 12)
      • J.S. Lai , B.-M. Song , R. Zhou , A.R. Hefner , D.W. Berning , C.-C. Shen . Characteristics and utilisation of a new class of low on-resistance MOS-gated power device. IEEE Trans. Ind. Appl. , 1282 - 1289

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