Design of on-chip error correction systems for multilevel NOR and NAND flash memories

F. Sun; S. Devarajan; K. Rose; T. Zhang

Design of on-chip error correction systems for multilevel NOR and NAND flash memories

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Design of on-chip error correction systems for multilevel NOR and NAND flash memories

Author(s): F. Sun ; S. Devarajan ; K. Rose ; T. Zhang
DOI: 10.1049/iet-cds:20060275

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Author(s): F. Sun ¹ ; S. Devarajan ¹ ; K. Rose ¹ ; T. Zhang ¹
- Affiliations: 1: ECSE Department, Rensselaer Polytechnic Institute, Troy, USA
Source: Volume 1, Issue 3, June 2007, p. 241 – 249
DOI: 10.1049/iet-cds:20060275 , Print ISSN 1751-858X, Online ISSN 1751-8598

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The design of on-chip error correction systems for multilevel code-storage NOR flash and data-storage NAND flash memories is concerned. The concept of trellis coded modulation (TCM) has been used to design on-chip error correction system for NOR flash. This is motivated by the non-trivial modulation process in multilevel memory storage and the effectiveness of TCM in integrating coding with modulation to provide better performance at relatively short block length. The effectiveness of TCM-based systems, in terms of error-correcting performance, coding redundancy, silicon cost and operational latency, has been successfully demonstrated. Meanwhile, the potential of using strong Bose–Chaudhiri–Hocquenghem (BCH) codes to improve multilevel data-storage NAND flash memory capacity is investigated. Current multilevel flash memories store 2 bits in each cell. Further storage capacity may be achieved by increasing the number of storage levels per cell, which nevertheless will correspondingly degrade the raw storage reliability. It is demonstrated that strong BCH codes can effectively enable the use of a larger number of storage levels per cell and hence improve the effective NAND flash memory storage capacity up to 59.1% without degradation of cell programming time. Furthermore, a scheme to leverage strong BCH codes to improve memory defect tolerance at the cost of increased NAND flash cell programming time is proposed.

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Design of on-chip error correction systems for multilevel NOR and NAND flash memories

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