Dynamic models for substrate coupling in mixed-mode systems

Dynamic models for substrate coupling in mixed-mode systems

For access to this article, please select a purchase option:

Buy article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
IET Circuits, Devices & Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

In modern monolithic integrated circuits, substrate coupling is a major concern in mixed-mode systems design. Verification of such systems implies the availability of accurate and simulation-efficient substrate coupling models. Traditionally, for frequencies up to a few gigahertz, pure resistive models have been considered sufficient. However, with increasing frequencies of operation, dynamic models become mandatory. The authors motivate the use of dynamic resistive-capacitive (RC) models of substrate coupling as a natural extension to the standard purely resistive models. They propose an extraction methodology that starts with information about the process parameters and circuit's contact layout, and leads to a contact-to-contact RC element model. The underlying algorithm is based on a finite difference discretisation of the substrate, leading to a large tridimensional mesh which is reduced by means of a fast multigrid algorithm. Unlike standard model order reduction algorithms which can produce models of similar accuracy to state-space descriptions, the proposed method leads to a realisable RC model that can trivially be incorporated into circuit simulation tools. As a first approximation, such a model is shown to correspond to a single time-constant system. Furthermore, it is shown that this time constant can be computed from knowledge of the conductivity and permittivity of a single dominant layer. It is verified that this formulation can accurately model substrate coupling effects for frequencies up to several tens of gigahertz.


    1. 1)
    2. 2)
      • B.M.J. Kup , E.C. Dijkmans , P.J.A. Naus , J. Sneep . A bit-stream digital-to-analog converter with 18-b resolution. IEEE J. Solid-State Circuits , 12 , 1757 - 1763
    3. 3)
      • Gharpurey, R.: `Modeling and analysis of substrate coupling in integrated circuits', June 1995, PhD, University of California at Berkeley, Department of Electrical Engineering and Computer Science, Berkeley, CA.
    4. 4)
    5. 5)
      • Verghese, N.: `Extraction and simulation techniques for substrate-coupled noise in mixed-signal integrated circuits', August 1995, PhD, Carnegie Mellon University, Department of Electrical and Computer Engineering, Pittsburgh, PA.
    6. 6)
      • T.A. Johnson , R. Knepper , V. Marcellu , W. Wang . Chip substrate resistance modeling technique for integrated circuit design. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. , 2 , 126 - 134
    7. 7)
      • Nauta, B., Hoogzaad, G.: `How to deal with substrate noise in analog CMOS circuits', European. Conf. on Circuit Theory and Design, September 1997, Budapest, Hungary, p. 1–6, Late 12:.
    8. 8)
    9. 9)
      • van Genderen, A.J., van der Meijs, N.P., Smedes, T.: `Fast computation of substrate resistances in large circuits', European Design and Test Conf., February 1996, Paris, p. 560–565.
    10. 10)
      • Mitra, S., Rutenbar, R.A., Carley, L.R., Allstot, D.J.: `A methodology for rapid estimation of substrate-coupled switching noise', IEEE 1995 Custom Integrated Circuits Conf., 1995, p. 129–132.
    11. 11)
      • Phillips, J.R., Silveira, L.M.: `Simulation approaches for strongly coupled interconnect systems', Int. Conf. on Computer Aided-Design, November 2001, p. 430–437.
    12. 12)
      • Smedes, T., van der Meijs, N.P., van Genderen, A.J.: `Extraction of circuit models for substrate cross-talk', Int. Conf. on Computer Aided-Design, November 1995, San Jose, CA, p. 199–206.
    13. 13)
      • Gharpurey, R., Meyer, R.G.: `Modeling and analysis of substrate coupling in integrated circuits', IEEE 1995 Custom Integrated Circuits Conf., 1995, p. 125–128.
    14. 14)
      • Verghese, N.K., Allstot, D.J.: `SUBTRACT: a program for the efficient evaluation of substrate parasitics in integrated circuits', Int. Conf. on Computer Aided-Design, November 1995, San Jose, CA.
    15. 15)
      • Costa, J.P., Chou, M., Silveira, L.M.: `Efficient techniques for accurate modeling and simulation of substrate coupling in mixed-signal IC's', Design, Automation and Test in Europe, Exhibition and Conf., February 1998, Paris, France, p. 892–898.
    16. 16)
      • Chou, M., White, J.: `Multilevel integral equation methods for the extraction of substrate coupling parameters in mixed-signal IC's', 35thACM/IEEE Design Automation Conf., June 1998, p. 20–25.
    17. 17)
      • Kanapka, J., Phillips, J., White, J.: `Fast methods for extraction and sparsification of substrate coupling', Proc. 37th ACM/IEEE Design Automation Conf., June 2000.
    18. 18)
      • Clement, F.J.R., Kayal, E.Z.M., Declercq, M.: `Layin: toward a global solution for parasitic coupling modeling and visualization', Proc. IEEE Custom Integrated Circuit Conf., May 1994, p. 537–540.
    19. 19)
      • Wemple, I.L., Yang, A.T.: `Mixed-signal switching noise analysis using Voronoi-tesselation substrate macromodels', 32ndACM/IEEE Design Automation Conf., June 1995, San Francisco, CA, p. 439–444.
    20. 20)
    21. 21)
      • L.M. Silveira , N. Vargas . Characterizing substrate coupling in deep sub-micron designs. IEEE Des. Test Comput. , 2 , 4 - 15
    22. 22)
      • J.M.S. Silva , L. Miguel Silveira . Substrate model extraction using finite differences and parallel multigrid. Integr. VLSI J. , 447 - 460
    23. 23)
      • Chen, T.-H., Luk, C., Chen, C.C.-P.: `SuPREME: substrate and power-delivery reluctance-enhanced macromodel evaluation', Int. Conf. on Computer Aided-Design, November 2003, San Jose, CA, p. 786–792.
    24. 24)
      • Gharpurey, R., Hosur, S.: `Transform domain techniques for efficient extraction of substrate parasitics', Proc. Int. Conf. on Computer-Aided Design, November 1997, p. 461–467.
    25. 25)
      • M. Pfost , H.-M. Rein . Modeling and measurement of substrate coupling in si-bipolar IC's up to 40 ghz. IEEE J. Solid-State Circuits , 4 , 582 - 591
    26. 26)
      • Lan, H., Yu, Z., Dutton, R.W.: `A CAD-oriented modeling approach of frequency-dependent behavior of substrate noise coupling for mixed-signal IC design', Fourth Int. Symp. on Quality Electronic Design, 2003, March 2003, p. 195–200.
    27. 27)
      • Li, H., Carballido, J., Yu, H.H., Okhmatovski, V.I., Rosenbaum, E., Cangellaris, A.C.: `Comprehensive frequency-dependent substrate noise analysis using boundary element method', Int. Conf. on Computer-Aided Design, November 2002, San Jose, CA, p. 2–9.
    28. 28)
      • Xu, C., Fiez, T., Mayaram, K.: `High Frequency Lumped Element Models for Substrate Noise Coupling', IEEE Int. Workshop on Behavioral Modeling and Simulation, October 2003, p. 47–50.
    29. 29)
      • P. Feldmann , R.W. Freund . Efficient linear circuit analysis by Padé approximation via the Lanczos process. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. , 5 , 639 - 649
    30. 30)
      • L.M. Silveira , M. Kamon , J.K. White . Algorithms for coupled transient simulation of circuits and complicated 3-D packaging. IEEE Trans. Compon. Packag. Manuf. Technol. B, Adv. Packag. , 1 , 92 - 98
    31. 31)
    32. 32)
      • Grimme, E.: `Krylov projection methods for model reduction', 1997, PhD, University of Illinois at Urbana-Champaign, Coordinated-Science Laboratory, Urbana-Champaign, IL.

Related content

This is a required field
Please enter a valid email address