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Low-power differential coefficients-based FIR filters using hardware-optimised multipliers

Low-power differential coefficients-based FIR filters using hardware-optimised multipliers

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A minimal-difference differential coefficients method is presented for low power and high-speed realisation of differential-coefficients-based finite impulse response filters. The conventional differential coefficients method (DCM) uses the difference between adjacent coefficients whereas we identify the coefficients that have the least difference between their magnitude values and use these minimal difference values to encode the differential coefficients. Our minimal-difference differential coefficients can be coded using fewer bits, which in turn reduces the number of full additions required for coefficient multiplication. By employing a differential-coefficient partitioning algorithm and a pseudofloating-point representation, we show that the number of full adders and the net memory needed to implement the coefficient multipliers can be significantly reduced. The proposed method is combined with common subexpression elimination for further reduction of complexity. Experimental results show the average reductions of full adder, memory and energy dissipated achieved by our method over the DCM are 40, 35 and 50%, respectively.

References

    1. 1)
    2. 2)
    3. 3)
    4. 4)
    5. 5)
      • Mehendale, M., Sherlekar, S.D., Venkatesh, G.: `Synthesis of multiplierless FIR filters with minimum number of additions', Proc. 1995 IEEE/ACM Int. Conf. on Computer-Aided Design, 1995, p. 668-671.
    6. 6)
    7. 7)
      • M. Yagyu , A. Nishihara , N. Fuji . Fast FIR digital filter structures using minimal number of adders and its application to filter design. ICICE Trans. Fundam. Electron. Commun. Comput. Sci. , 8 , 1120 - 1129
    8. 8)
      • R. Pasko , P. Schaumont , V. Derudder , S. Vernalde , D. Durackova . A new algorithm for elimination of common subexpressions. IEEE Trans. Comput.-Aided Des. Integ. Circuits Syst. , 1 , 58 - 68
    9. 9)
      • Xu, F., Chang, C.-H., Jong, C.-C.: `Efficient algorithms for common subexpression elimination in digital filter design', Proc. IEEE Int. Conf. on Acoustics, Speech, and Signal Processing, May 2004, 5, p. 137–140.
    10. 10)
    11. 11)
      • N. Sankarayya , K. Roy , D. Bhattacharya . Algorithms for low power and high speed FIR filter realization using differential coefficients. IEEE Trans. Circuits Syst. II , 487 - 497
    12. 12)
    13. 13)
      • Erdogan, A.T., Arslan, T., Lai, R.: `Implementation of the decorrelating transformation for low power FIR filters', Proc. IEEE Workshop on Signal Processing Systems, 2004, p. 337–342.
    14. 14)
      • Lee, I-H., Wu, C-S., Wu, A-Y.: `Coefficient multiplierless FIR filter structure based on modified DECOR transformation', Proc. IEEE Int. Conf. on Acoustics, Speech, and Signal Processing, 1999, p. 1065–1068, vol. 2.
    15. 15)
    16. 16)
      • Vinod, A.P., Lai, E.M-K.: `Optimizing vertical common subexpression elimination using coefficient-partitioning for designing low complexity software radio channelizers', Proc. IEEE Int. Symp. on Circuits and Systems, 2005, p. 5429–5432.
    17. 17)
      • J.G. Proakis , D.G. Manolakis . (1996) Digital signal processing principles, algorithms, and applications.
    18. 18)
      • Vinod, A.P., Premkumar, A.B., Lai, E.M-K.: `An optimal entropy coding scheme for efficient implementation of pulse shaping FIR filters in digital receivers', Proc. IEEE Int. Symp on Circuits and Systems, 2003, 4, p. 229–232.
    19. 19)
      • T. Burd . (1994) Low-power CMOS library design methodology.
    20. 20)
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