Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

Accurate and computer efficient modelling of single event transients in CMOS circuits

Accurate and computer efficient modelling of single event transients in CMOS circuits

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Circuits, Devices & Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

A new analytical modelling approach to evaluate the impact of single event transients (SETs) on CMOS circuits has been developed. The model allows evaluation of transient pulse amplitude and width (duration) at the logic level, without the need to run circuit level (Spice-like) simulations. The SET mechanism in MOS circuits is normally investigated by Spice-like circuit simulation. The problem is that electrical simulation is time-consuming and must be performed for each different circuit topology, incident particle and track. The availability of a simple model at the logic gate level may greatly improve circuit sensitivity analysis. The electrical response of a circuit to an ionising particle hit depends on many parameters, such as circuit topology, circuit geometry and waveform shape of the charge injection mechanism. The proposed analytical model, which is accurate and computer efficient, captures these transistor-level effects of ionising particle hits and models them to the logic level of abstraction. The key idea is to exploit a model that allows the rapid determination of the sensitivity of any logic gate in a CMOS circuit, without the need to run circuit simulations. The model predicts whether or not a particle hit generates a SET, which may propagate to the next logic gate or memory element, making possible to analyse the sensitivity of each node in a complex circuit. Model derivation is strongly related to circuit electrical behaviour, being consistent with technology scaling. The model is suitable for integration into CAD tools, intending to make automated evaluation of circuit sensitivity to SET possible, as well as automated estimation of soft error rate.

References

    1. 1)
      • T. Calvin , F. Vargas , M. Nicolaidis , R. Velazco . A low-cost, highly reliable SEU-tolerant SRAM: prototype and test results. IEEE Trans. Nucl. Sci. , 1592 - 1598
    2. 2)
      • Shivakumar, P., Kistler, M., Keckler, S.W., Burger, D., Alvisi, L.: `Modelling the effect of technology trends on the soft error rate of combinational logic', Int. Conf. on Dependable Systems and Networks 2002, 2001, Proceedings IEEE Computer Society, Piscataway, p. 389–398.
    3. 3)
    4. 4)
      • G.I. Wirth , M.G. Vieira , F.G. Kastensmidt . (2005) Computer efficient modeling of SRAM cell sensitivity to SEU, Proc. IEEE Latin American Test Workshop.
    5. 5)
      • http://www.austriamicrosystems.com.
    6. 6)
      • J.F. Ziegler . Terrestrial cosmic rays. IBM J. Res. Dev. , 1 , 19 - 40
    7. 7)
      • K. Castellani-Coulié , J.M. Palau , G. Hubert , M.C. Calvet , P.E. Dodd , F. Sexton . Various SEU conditions in SRAM atudied by 3-D device Simulation. IEEE Trans. Nucl. Sci. , 1931 - 1936
    8. 8)
      • http://www-device.eecs.berkeley.edu.
    9. 9)
      • P. Liden , P. Dahlgren , R. Johansson , J. Karlsson . (1994) On latching probability of particle induced transients in combinational networks.
    10. 10)
      • G.R. Srinivasan . Modelling the cosmic-ray-induced soft-error rate in integrated circuits: an overview. IBM J. Res. Dev. , 1 , 77 - 90
    11. 11)
    12. 12)
      • P. Hazucha , C. Svensson , S. Wender . Cosmic-ray soft error characterization of a standard 0.6-µm CMOS process. IEEE J. Solid State Circuits , 1422 - 1429
    13. 13)
    14. 14)
      • Palau, J.M., Calvet, M.C., Dodd, P.E., Sexton, F.W., Roche, P.: `Contribution of device simulation to SER understanding', 41stIEEE Int. Reliability Physics Symp., 2003, Dallas, TX, p. 71–75.
    15. 15)
      • G.C. Messenger . Collection of charge on junction nodes from ion tracks. IEEE Trans. Nucl. Sci. , 2024 - 2031
    16. 16)
      • Cha, H., Patel, J.H.: `A Logic-level model for alpha-particle hits in CMOS circuits', Proc. IEEE Int. Conf. on Computer Design, 1993, p. 538–542.
    17. 17)
      • H. Weste , K. Eshraghian . (1992) Principles of CMOS VLSI design: a systems perspective.
    18. 18)
    19. 19)
      • Alexandrescu, D., Anghel, L., Nicolaidis, M.: `New methods for evaluating the impact of single event transients in VDSM ICs', 7thIEEE Int. Symp. on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002, Vancouver, BC, Canada, p. 99–107.
    20. 20)
      • Hirata, A., Onodera, H., Tamaru, K.: `Proposal of a timing model for CMOS logic gates driving a CRC load', Proc. 1998 IEEE/ACM Int. Conf. on Computer-Aided Design San Jose, CA, 1998, p. 537–544.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds_20050210
Loading

Related content

content/journals/10.1049/iet-cds_20050210
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address