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access icon free All-digital power-efficient integrating frequency difference-to-digital converter for GHz frequency-locking

This study presents an all-digital power-efficient integrating frequency difference-to-digital converter (iFDDC) and explores its applications in gigahertz (GHz) frequency-locking. The iFDDC utilises a bi-directional gated delay line (BDGDL) to detect and accumulate the frequency difference between two GHz signals and digitises the result with ultra-low power consumption. The built-in integration of the iFDDC ensures that the in-band quantisation noise of the BDGDL and digital controlled oscillator (DCO) is first-order suppressed. The all-digital realisation of the iFDDC makes it fully compatible with technology scaling. The effectiveness of the proposed iFDDC is verified using the simulation results of a 5 GHz frequency-locked loop designed in a Taiwan Semiconductor Manufacturing Company (TSMC) 65 nm 1.2 V complementary metal-oxide-semiconductor (CMOS). The iFDDC consumes only 474 µW, offering the lowest power/frequency efficiency among reported FDDCs. The DCO locks to 5 GHz reference in <10 cycles.

http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2020.0039
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content/journals/10.1049/iet-cds.2020.0039
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