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access icon free Low-power, high-linearity transconductor with a high tolerance for process and temperature variations

  • Author(s): Jing Zhao 1 ; Yichuang Sun 2 ; Guigen Nie 1 ; Oluyomi Simpson 2 ; Weilin Xu 3
    • View affiliations
  • Source: Volume 14, Issue 8, November 2020, p. 1295 – 1304
    DOI:  10.1049/iet-cds.2019.0565 , Print ISSN 1751-858X, Online ISSN 1751-8598
© The Institution of Engineering and Technology
Received 08/01/2020, Accepted 21/08/2020, Revised 09/08/2020, Published 16/10/2020

A novel scheme for tunable complementary metal–oxide–semiconductor (CMOS) transconductor robust against process and temperature (PT) variations is presented. The proposed configuration is a voltage controlled circuit based on a double negative channel-metal-oxide-semiconductor (NMOS) transistor differential pairs connected in parallel, which has low power and high linearity. The PT compensation is completed by two identical PT compensation bias voltage generators (PTCBVGs), which can guarantee the designed transconductor high tolerance for PT variations. A complete CMOS transconductor with PTCBVG has been designed and simulated using 0.18 μm technology. The effectiveness of PT compensation technique is proved. The simulation results of post-layout are commensurate with pre-layout. Post-layout simulation results show that when temperature changes from − 40 to 85°C for different process corners (TT, SS, SF, FS and FF), the transconductance varies from 91.8 to 123.6 μS, the temperature coefficient is <1090 ppm/°C, the total harmonic distortion is from  − 78 to −72dB at 1 MHz for 0.2 VPP input signal, −3 dB bandwidth changes from 2.5 to 5 GHz, input-referred noise varies from 78.1 to 124.8 nV/sqartHz at 1 MHz and DC power is from 1.5 to 3.2 mW.

Inspec keywords: integrated circuit modelling; low-power electronics; CMOS integrated circuits; harmonic distortion; integrated circuit layout; compensation

Other keywords: PT variations; temperature coefficient; tunable CMOS transconductor; PTCBVG; size 0.18 mum; process and temperature variations; temperature -40.0 degC to 85.0 degC; frequency 2.5 GHz to 5.0 GHz; input-referred noise; PT compensation bias voltage generators; DC power; voltage controlled circuit; total harmonic distortion; double NMOS transistor differential pairs; transconductor high tolerance; post-layout simulation results; conductance 91.8 muS to 123.6 muS; frequency 1.0 MHz; complementary metal-oxide-semiconductor; power 1.5 mW to 3.2 mW; high-linearity transconductor; low-power transconductor

Subjects: Electrical/electronic equipment (energy utilisation); CMOS integrated circuits; Semiconductor integrated circuit design, layout, modelling and testing

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