© The Institution of Engineering and Technology
In this study, the design routine of a novel phase frequency detector and charge-pump (PFD-CP) is discussed. The main advantage of the proposed circuit is its improved dead zone performance as the circuits of PFD-CP have been merged to reduce the latency of the structure. To justify this, by means of a reconfigurable loop filter, a fast-locking low-power phase-locked loop (PLL) has been implemented which can operate at the range of 100 MHz–1.2 GHz while its power consumption is 2.53 mW at 1.2 GHz operating frequency. The whole PLL is implemented in 0.18 µm complementary metal–oxide–semiconductor technology with a 1.8 V power supply. The post-layout simulation results are provided to show the conformity of theoretical assumptions and circuit-level implementations which depict the locking time of 0.54 µs at 1.2 GHz operating frequency.
References
-
-
1)
-
41. Liu, W., Li, W., Ren, P., et al: ‘A PVT tolerant 10 to 500 MHz all-digital phase-locked loop with coupled TDC and DCO’, IEEE J. Solid-State Circuits, 2010, 45, (2), pp. 314–321.
-
2)
-
40. Chen, M.S.-W., Su, D., Mehta, S.: ‘A calibration-free 800 MHz fractional-N digital PLL with embedded TDC’, IEEE J. Solid-State Circuits, 2010, 45, (12), pp. 2819–2827.
-
3)
-
20. Gholami, M.: ‘Phase detector with minimal blind zone and reset time for GSamples/s DLLs’, Circuits Syst. Signal Process., 2017, 36, (9), pp. 3549–3563.
-
4)
-
9. Zhao, B., Yan, D.L.: ‘A low-power digital design of all digital PLL for 2.4 G wireless communication applications’. 2016 Int. Symp. on Integrated Circuits (ISIC), Singapore, 2016, pp. 1–4.
-
5)
-
23. Brennan, P.V.: ‘Phase-locked loops: principles and practice’ (Macmillan International Higher Education, 1996).
-
6)
-
10. Can, S., Sahinkaya, Y.E.: ‘Modeling and simulation of an analog charge-pump phase locked loop’, Simulation, 1988, 50, (4), pp. 155–160.
-
7)
-
16. Lei, F., White, M.H.: ‘Reference injected phase-locked loops (PLL-RIs)’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2017, 64, (7), pp. 1651–1660.
-
8)
-
31. Lip-Kai, S., Sulaiman, M.-S., Yusoff, Z.: ‘Fast-lock dual charge pump analog DLL using improved phase frequency detector’. 2007 Int. Symp. on VLSI Design, Automation and Test (VLSI-DAT), Taiwan, 2007, pp. 1–5.
-
9)
-
27. Hwang, M.-S., Kim, J., Jeong, D.-K.: ‘Reduction of pump current mismatch in charge-pump PLL’, Electron. Lett., 2009, 45, (3), pp. 135–136.
-
10)
-
15. Ikeda, S., Lee, S., Ito, H., et al: ‘A 0.5 V 5.96-GHz PLL with amplitude-regulated current-reuse VCO’, IEEE Microw. Wirel. Compon. Lett., 2017, 27, (3), pp. 302–304.
-
11)
-
8. Wu, Y., Shahmohammadi, M., Chen, Y., et al: ‘A 3.5–6.8-GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ-TDC for low in-band phase noise’, IEEE J. Solid-State Circuits, 2017, 52, (7), pp. 1885–1903.
-
12)
-
39. Chang, R.C., Kuo, L.-C., Chen, H.-M.: ‘A low-voltage low-power CMOS phase-locked loop’, J. Circuits Syst. Comput., 2005, 14, (5), pp. 997–1006.
-
13)
-
17. Mansuri, M., Liu, D., Yang, C.-K.K.: ‘Fast frequency acquisition phase-frequency detectors for GSa/s phase-locked loops’. Proc. 27th European Solid-State Circuits Conf., Austria, 2001, pp. 333–336.
-
14)
-
22. Egan, W.F.: ‘Frequency synthesis by phase lock’ (Wiley-Interscience, New York, 1981), p. 295.
-
15)
-
28. Zadeh, L.A.: ‘Fuzzy sets’, Inf. Control, 1965, 8, (3), pp. 338–353.
-
16)
-
6. Wu, W., Bai, X., Staszewski, R.B., et al: ‘A 56.4-to-63.4 GHz spurious-free all-digital fractional-N PLL in 65 nm CMOS’. 2013 IEEE Int. Solid-State Circuits Conf. Digest of Technical Papers, San Francisco, CA, USA, 2013, pp. 352–353.
-
17)
-
35. Chen, W.-H., Inerowicz, M.E., Jung, B.: ‘Phase frequency detector with minimal blind zone for fast frequency acquisition’, IEEE Trans. Circuits Syst. II, Express Briefs, 2010, 57, (12), pp. 936–940.
-
18)
-
30. Johansson, H.O.: ‘A simple precharged CMOS phase frequency detector’, IEEE J. Solid-State Circuits, 1998, 33, (2), pp. 295–299.
-
19)
-
18. Strzelecki, J., Ren, S.: ‘Near-zero dead zone phase frequency detector with wide input frequency difference’, Electron. Lett., 2015, 51, (14), pp. 1059–1061.
-
20)
-
14. Cho, H., Seong, K., Choi, K.-H., et al: ‘8.7 A 0.0047 mm 2 highly synthesizable TDC-and DCO-less fractional-N PLL with a seamless lock range of f REF to 1 GHz’. 2017 IEEE Int. Solid-State Circuits Conf. (ISSCC), San Francisco, CA, USA, 2017, pp. 154–155.
-
21)
-
11. Bluestone, A., Kaveh, R., Theogarajan, L.: ‘An analog phase prediction based fractional-N PLL’. 2017 IEEE Int. Symp. on Circuits and Systems (ISCAS), USA, 2017, pp. 1–4.
-
22)
-
2. Best, R.E.: ‘Phase locked loops: design, simulation, and applications’ (McGraw-Hill Professional, 2007).
-
23)
-
37. Fathi, A., Mousazadeh, M., Khoei, A.: ‘High-speed, low power, and dead zone improved phase frequency detector’, IET Circuits Devices Syst., 2019, 13, (7), pp. 1056–1062.
-
24)
-
7. Lee, J.-Y., Park, M.-J., Min, B.-H., et al: ‘A 4-GHz all digital PLL with low-power TDC and phase-error compensation’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2012, 59, (8), pp. 1706–1719.
-
25)
-
34. He, Y., Cui, X., Lee, C.L., et al: ‘An improved fast acquisition PFD with zero blind zone for the PLL application’. 2014 IEEE Int. Conf. on Electron Devices and Solid-State Circuits, USA, 2014, pp. 1–2.
-
26)
-
4. Lee, S.-K., Seo, Y.-H., Park, H.-J., et al ‘A 1 GHz ADPLL with a 1.25 ps minimum-resolution sub-exponent TDC in 0.18 μm CMOS’, IEEE J. Solid-State Circuits, 2010, 45, (12), pp. 2874–2881.
-
27)
-
38. Kester, W.: ‘Converting oscillator phase noise to time jitter’. , 2009.
-
28)
-
32. Fu, Z., Wang, X., Minh, E., et al: ‘A fast acquisition phase frequency detector for phase-locked loops’. 2008 Argentine School of Micro-Nanoelectronics, Technology and Applications, Argentina, 2008, pp. 77–80.
-
29)
-
13. Hussein, A., Vasadi, S., Soliman, M., et al: ‘19.3 A 50-to-66 GHz 65 nm CMOS all-digital fractional-N PLL with 220fs rms jitter’. 2017 IEEE Int. Solid-State Circuits Conf. (ISSCC), San Francisco, CA, USA, 2017, pp. 326–327.
-
30)
-
36. Koithyar, A., Ramesh, T.K.: ‘A faster phase frequency detector using transmission gate–based latch for the reduced response time of the PLL’, Int. J. Circuit Theory Appl., 2018, 46, (4), pp. 842–854.
-
31)
-
5. Tasca, D., Zanuso, M., Marzin, G., et al: ‘A 2.9–4.0-GHz fractional-N digital PLL with bang-bang phase detector and 560-fsrms integrated jitter at 4.5-mW power’, IEEE J. Solid-State Circuits, 2011, 46, (12), pp. 2745–2758.
-
32)
-
1. Staszewski, R.B., Wallberg, J.L., Rezeq, S., et al: ‘All-digital PLL and transmitter for mobile phones’, IEEE J. Solid-State Circuits, 2005, 40, (12), pp. 2469–2482.
-
33)
-
42. Chung, C.-C., Lee, C.-Y.: ‘An all-digital phase-locked loop for high-speed clock generation’, IEEE J. Solid-State Circuits, 2003, 38, (2), pp. 347–351.
-
34)
-
24. Bianchi, G.: ‘Phase-locked loop synthesizer simulation’ (McGraw-Hill, Inc., 2005).
-
35)
-
21. Fernandez, D., Manandhar, S.: ‘Digital phase locked loop (PDF)’. , 8 December 2003.
-
36)
-
3. Staszewski, R.B., Hung, C.-M., Maggio, K., et al: ‘All-digital phase-domain TX frequency synthesizer for bluetooth radios in 0.13/spl mu/m CMOS’. 2004 IEEE Int. Solid-State Circuits Conf. (IEEE Cat. No. 04CH37519), San Francisco, CA, USA, 2004, pp. 272–527.
-
37)
-
12. Koskin, E., Blokhina, E., Shan, C., et al: ‘Discrete-time modelling and experimental validation of an all-digital PLL for clock-generating networks’. 2016 14th IEEE Int. New Circuits and Systems Conf. (NEWCAS), Canada, 2016, pp. 1–4.
-
38)
-
26. Han-il, L., Tae-won, A., Duck-young, J., et al: ‘Scheme for no dead zone, fast PFD design’, J. Korean Phys. Soc., 2002, 40, p. 543.
-
39)
-
29. Jovanovic, G., Stojcev, M., Stamenkovic, Z.: ‘A CMOS voltage controlled ring oscillator with improved frequency stability’, Scientific Publications of the State University of Novi Pazar, Series A: Appl. Math. Informat. Mech., 2010, 2, (1), pp. 1–9.
-
40)
-
19. Hu, W., Chunglen, L., Wang, X.: ‘Fast frequency acquisition phase-frequency detector with zero blind zone in PLL’, Electron. Lett., 2007, 43, (19), pp. 1018–1020.
-
41)
-
33. Khare, K., Khare, N., Deshpande, P., et al: ‘Phase frequency detector of delay locked loop at high frequency’. 2008 IEEE Int. Conf. on Semiconductor Electronics, Malaysia, 2008, pp. 113–116.
-
42)
-
43. Wang, S.-H., Hung, C.-C.: ‘A 0.35-V 240-μW fast-lock and low-phase-noise frequency synthesizer for implantable biomedical applications’, IEEE Trans. Biomed. Circuits Syst., 2019, 13, (6), pp. 1759–1770.
-
43)
-
25. Gao, X., Klumperink, E.A.M., Bohsali, M., et al: ‘A low noise sub-sampling PLL in which divider noise is eliminated and PD/CP noise is not multiplied by N2’, IEEE J. Solid-State Circuits, 2009, 44, (12), pp. 3253–3263.
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