access icon free Evanescent mode based compact modelling of a dual-metal double-gate tunnel field-effect transistor

© The Institution of Engineering and Technology
Received 07/12/2019, Accepted 28/07/2020, Revised 16/07/2020, Published 17/08/2020

In this study, channel potential for silicon-based doped dual-metal double-gate tunnel field-effect transistor structure is analytically solved using the evanescent-mode approach in the sub-threshold region. This method generally describes short channel effects in the entire channel region of the device structure and predicts different characteristic length which depends on tunnel current and does not depend along a transverse direction within the channel. The model is valid for the whole device structure rather than just semiconductor/insulator interfaces. The impact of variation of bias condition on channel potential is also investigated in the sub-threshold region. Finally, drain current is evaluated using Kane's and Kleysh's model and validated with a calibrated simulation, which has been carried out using 2D TCAD Sentaurus simulator.

Inspec keywords: tunnel field-effect transistors; technology CAD (electronics); elemental semiconductors; semiconductor device models; silicon

Other keywords: bias condition; 2D TCAD Sentaurus simulator; compact modelling; sub-threshold region; Kleysh model; drain current; channel potential; evanescent-mode approach; tunnel current; silicon-based doped double-gate tunnel field-effect transistor structure; Kane model; channel region; characteristic length; Si; short channel effects; device structure

Subjects: Semiconductor device modelling, equivalent circuits, design and testing; Other field effect devices

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