Fast Fourier transform (FFT) is utilised to minimise the complexity of discrete Fourier transform by converting signals from frequency domain to time domain and conversely. Digital signal processing systems like image processing, general filtering, sonar, spread-spectrum communications and convolutions use this FFT operations. Radix-2 decimation in frequency (R2DIF) method is designed to execute an efficient FFT architecture in this study. Each and every state of the FFT stores the input and output the data using the R2DIF method. Also, the complex twiddle factors in FFT are replaced by the proposed uniform Montgomery algorithm. This technique simply performs the shift-add method instead of the multiplication process which also enhances the convergence of the calculation. So, the FFT implementation is done with the help of the proposed method which reduces the usage of chips in the process. Based on this approach, it performs the operation of FFT from 16 points to 1024 points and the performance of this proposed method is compared with existing approaches. Moreover, it does not require expensive dedicated functional blocks and uses only distributed logic resources. The simulation is carried out by the Xilinx platform using Verilog coding. The proposed design outperforms conventional methods in terms of less usage power and high speed.

References

1. 1)
  - 15. Nguyen, N.H., Khan, S.A., Kim, C.-H., et al: ‘A high-performance, resource-efficient, reconfigurable parallel-pipelined FFT processor for FPGA platforms’, Microprocess. Microsyst., 2018, 60, pp. 96–106, doi:10.1016/j.micpro.2018.04.003.
2. 2)
  - 32. Xiao, H., Yin, X., Wu, N., et al: ‘VLSI design of low-cost and high-precision fixed-point reconfigurable FFT processors’, IET Comput. Digit. Tech., 2018, 12, (3), pp. 105–110.
3. 3)
  - 28. Dai, W., Chen, D.D., Cheung, R.C., et al: ‘Area-time efficient architecture of FFT-based montgomery multiplication’, IEEE Trans. Comput., 2016, 66, (3), pp. 375–388.
4. 4)
  - 30. Chandu, Y., Maradi, M., Manjunath, A., et al: ‘Optimized high speed radix-8 FFT algorithm implementation on FPGA’. 2018 2nd Int. Conf. on Trends in Electronics and Informatics (ICOEI), Tirunelveli, India, 11 May 2018, pp. 430–435.
5. 5)
  - 4. Derafshi, Z.H., Frounchi, J., Taghipour, H.: ‘A high speed FPGA implementation of a 1024-point complex FFT processor’. 2010 Second Int. Conf. on Computer and Network Technology, Bangkok, Thailand, 2010, doi:10.1109/iccnt.2010.12.
6. 6)
  - 23. Dinh, P.T.K., Dinh, L.T.T., Tran, H.V., et al: ‘Hardware design and optimization of multimode pipeline based FFT for IEEE 802.11ax WLAN devices’. 2018 IEEE Seventh Int. Conf. on Communications and Electronics (ICCE), Hue, Vietnam, 2018, doi:10.1109/cce.2018.8465752.
7. 7)
  - 16. Hassan, S.L.M., Sulaiman, N., Halim, I.S.A.: ‘Low power pipelined FFT processor architecture on FPGA’. 2018 9th IEEE Control and System Graduate Research Colloquium (ICSGRC), Shah Alam, Malaysia, 2018, doi:10.1109/icsgrc.2018.8657583.
8. 8)
  - 12. Sun, Z., Liu, X., Ji, Z.: ‘The design of radix-4 FFT by FPGA’. 2008 Int. Symp. on Intelligent Information Technology Application Workshops, Shanghai, China, 2008.
9. 9)
  - 31. Saldamli, G., Baek, Y.J.: ‘Uniform montgomery multiplier’, J. Cryptograph. Eng., 2019, 9, pp. 333–339.
10. 10)
  - 27. Elango, K., Muniandi, K.: ‘Hardware implementation of FFT/IFFT algorithms incorporating efficient computational elements’, J. Electr. Eng. Technol., 2019, 14, (4), pp. 1717–1721.
11. 11)
  - 11. Jung, Y., Cho, J., Lee, S., et al: ‘Area-efficient pipelined FFT processor for zero-padded signals’, Electronics, 2019, 8, (12), p. 1397, doi:10.3390/electronics8121397.
12. 12)
  - 29. Akkad, G., Mansour, A., ElHassan, B., et al: ‘Twiddle factor generation using Chebyshev polynomials and HDL for frequency domain beamforming’. Int. Conf. on Applications in Electronics Pervading Industry, Environment and Society, Springer, Cham, 26 September 2018, pp. 153–165.
13. 13)
  - 25. Zhang, X., Chen, X., Zhang, Y.: ‘Small area high speed configurable FFT processor’. 2019 Int. Conf. on IC Design and Technology (ICICDT), SUZHOU, China, June 2019, pp. 1–4.
14. 14)
  - 17. Nguyen, N.-H., Khan, S.A., Kim, C.-H., et al: ‘An FPGA-based implementation of a pipelined FFT processor for high-speed signal processing applications’, Applied Reconfigurable Computing, The Netherlands, 2017, pp. 81–89, doi: 10.1007/978-3-319-56258-2_8.
15. 15)
  - 24. Nori, S.M., Dawwd, S.A.: ‘Reduced area and low power implementation of FFT/IFFT processor’, Iraqi J. Electr. Electron. Eng., 2018, 14, (2), pp. 108–119.
16. 16)
  - 20. Kumar, V., Selvakumar, D., Sobha, P.M.: ‘Area and frequency optimized 1024 point radix-2 FFT processor on FPGA’. 2015 Int. Conf. on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA), Bangalore, India, 2015, doi:10.1109/vlsisata.2015.7050487.
17. 17)
  - 18. Tang, T., Pan, J., Yang, D., et al: ‘Frequency measurement by FFT based on FPGA’. 2018 IEEE 3rd Advanced Information Technology, Electronic and Automation Control Conf. (IAEAC), Chongqing, China, 2018, doi:10.1109/iaeac.2018.8577876.
18. 18)
  - 21. Nguyen, H., Khan, S., Kim, C.-H., et al: ‘A pipelined FFT processor using an optimal hybrid rotation scheme for complex multiplication: design, FPGA implementation and analysis’, Electronics, 2018, 7, (8), p. 137, doi:10.3390/electronics7080137.
19. 19)
  - 13. Belabed, T., Jemmali, S., Souani, C.: ‘FFT implementation and optimization on FPGA’. 2018 4th Int. Conf. on Advanced Technologies for Signal and Image Processing (ATSIP), Sousse, Tunisia, 2018, doi:10.1109/atsip.2018.8364454.
20. 20)
  - 10. Kee, H., Petersen, N., Kornerup, J., et al: ‘Systematic generation of FPGA-based FFT implementations’. 2008 IEEE Int. Conf. on Acoustics, Speech and Signal, Processing, Las Vegas, NV, USA, 2008.
21. 21)
  - 5. He, H., Guo, H.: ‘The realization of FFT algorithm based on FPGA co-processor’. 2008 Second Int. Symp. on Intelligent Information Technology Application, Los Alamitos, CA, USA, 2008, doi:10.1109/iita.2008.461.
22. 22)
  - 14. Abbas, Z.A., Sulaiman, N.B., Yunus, N.A.M., et al: ‘An FPGA implementation and performance analysis between radix-2 and radix-4 of 4096 point FFT’. 2018 IEEE 5th Int. Conf. on Smart Instrumentation, Measurement and Application (ICSIMA), Songkla, Thailand, 2018, doi:10.1109/icsima.2018.8688777.
23. 23)
  - 9. Lim, S.Y., Crosland, A.: ‘Implementing FFT in an FPGA co-processor Sheac Yee Lim Altera Corporation 101 Innovation Drive, San Jose, Andrew Crosland, 2004.
24. 24)
  - 22. Nguyen, H.N., Kim, C.-H., Kim, J.-M.: ‘An efficient pipelined feedback processor for computing a 1024-point FFT using distributed logic’. Advances in Computer Communication and Computational Sciences, Thailand, 2018, pp. 245–256, doi:10.1007/978-981-13-0341-8_23.
25. 25)
  - 7. Ouerhani, Y., Jridi, M., Alfalou, A.: ‘Implementation techniques of high-order FFT into low-cost FPGA’. 2011 IEEE 54th Int. Midwest Symp. on Circuits and Systems (MWSCAS), Seoul, South Korea, 2011.
26. 26)
  - 6. Duan, B., Wang, W., Li, X., et al: ‘Floating-point mixed-radix FFT core generation for FPGA and comparison with GPU and CPU’. 2011 Int. Conf. on Field-Programmable Technology, New Delhi, India, 2011.
27. 27)
  - 26. Elango, K., Muniandi, K.: ‘VLSI implementation of an area and energy efficient FFT/IFFT core for MIMO-OFDM applications’, Ann. Telecommun., 2019, 17, pp. 1–3.
28. 28)
  - 1. Saeed, A., Elbably, M., Abdelfadeel, G., et al: ‘Efficient FPGA implementation of FFT/IFFT processor’, Int. J. circuits, Syst. Signal Process., 2009, 3, (3), pp. 103–110.
29. 29)
  - 19. Akkad, G., Mansour, A., ElHassan, B., et al: ‘FFT radix-2 and radix-4 FPGA acceleration techniques using HLS and HDL for digital communication systems’. 2018 IEEE Int. Multidisciplinary Conf. on Engineering Technology (IMCET), Beirut, Lebanon, 2018, doi:10.1109/imcet.2018.8603064.
30. 30)
  - 8. Harikrishna, K., Rao, T.R., Labay, V.A.: ‘FPGA implementation of FFT algorithm for IEEE’, 2013, 802.16e (Mobile WiMAX).
31. 31)
  - 33. Bansal, M, Nakhate, S.: ‘Fast performance pipeline re-configurable FFT processor based on radix-2 2 for variable length N’, Int. J. Electr. Electron. Eng. Telecommun., 2019, 8, (3), pp. 163–170.
32. 32)
  - 3. Haveliya, A.: ‘Design and simulation of 32-point FFT using radix-2 algorithm for FPGA implementation’. 2012 Second Int. Conf. on Advanced Computing & Communication Technologies, Rohtak, Haryana, India, 2012.
33. 33)
  - 2. Ghouwayel, A., Louet, Y.: ‘FPGA implementation of a re-configurable FFT for multi-standard systems in software radio context’, IEEE Trans. Consum. Electron., 2009, 55, (2), pp. 950–958, doi:10.1109/tce.2009.5174479.

Design optimisation of multiplier-free parallel pipelined FFT on field programmable gate array

References

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