One selector-one resistor (1S-1R) configuration is desirable to use in conductive bridge resistive random-access memory (CBRAM) and resistive random-access memory (RRAM) crossbar arrays (CBAs) to reduce sneak path current. In this study, an analytical model of Ta2O5/TaOx/TiO2 selector device is developed and is integrated with RRAM model to demonstrate the acquired features of 1S-1R to reduce the sneak path current. The proposed selector model is developed by considering the electric field-driven tunnelling mechanisms co-exist in thin multi-layer devices such as direct and Fowler-Nordheim tunnelling. The simulated characteristics of proposed model shows high non-linearity (∼1600), high selectivity (∼10⁴), high current density (∼10⁷ A/cm²) and low off current (∼46 nA). Further, the proposed model is simulated with different top electrode metals and dielectric materials to demonstrate the formation of optimal stack for the desired application. Then, the proposed selector model (1S) is integrated with RRAM model (1R) and the compatibility of the devices is verified. Moreover, from the presented 1S-1R model, various parameters for the establishment of CBA such as read/write voltages for selected/unselected trails are predicted and substantial conditions for sneak path current reduction such as non-linearity, Roff/Ron ratio and off-current (10 nA) are also evaluated.

References

1. 1)
  - 25. Woo, J., Lee, D., Cha, E., et al: ‘Vertically stacked ReRAM composed of a bidirectional selector and CB-RAM for cross-point array applications’, IEEE Electron Device Lett., 2013, 34, (12), pp. 1512–1514.
2. 2)
  - 5. Ho, P.W.C., Hatem, F.O., Almurib, H.A.F., et al: ‘Comparison between Pt/TiO2 /Pt and Pt/TaO × /TaOY/Pt based bipolar resistive switching devices’, J. Semicond., 2016, 37, (6), p. 064001.
3. 3)
  - 10. Woo, J., Lee, W., Park, S., et al: ‘Multi-layer tunnel barrier (Ta2O5/TaOx/TiO2) engineering for bipolar RRAM selector applications’. Symp. on VLSI Technology, T168–T169, Kyoto, January 2013.
4. 4)
  - 43. Deng, Y., Huang, P., Chen, B., et al: ‘RRAM crossbar array with cell selection device: a device and circuit interaction study’, IEEE Trans. Electron Devices, 2013, 60, (2), pp. 719–726.
5. 5)
  - 6. Almurib, H.A.F., Kumar, T.N., Lombardi, F.: ‘Design and evaluation of a memristor-based look-up table for non-volatile field programmable gate arrays’, IET Circuits, Devices Syst., 2016, 10, (4), pp. 292–300.
6. 6)
  - 8. Yang, Y., Mathew, J., Ottavi, M., et al: ‘Novel complementary resistive switch crossbar memory write and read schemes’, IEEE Trans. Nanotechnol., 2015, 14, (2), pp. 346–357.
7. 7)
  - 4. Kaushik, B.K., Ajayan, J.: ‘Nanoscale devices: physics, modeling, and their application’ (CRC Press, New York, 2018).
8. 8)
  - 45. Song, B., Xu, H., Hai-Jun, L., et al: ‘Impact of threshold voltage variation on 1S1R crossbar array with threshold switching selectors’, Appl. Phys. A, 2017, 123, (356), pp. 1–7.
9. 9)
  - 7. Cassuto, Y., Kvatinsky, S., Yaakobi, E.: ‘Sneak-path constraints in memristor’. 2013 IEEE Int. Symp. on Information Theory, Istanbul, 2013, pp. 156–160.
10. 10)
  - 2. Jagath, A.L., Leong, C.H., Kumar, T.N., et al: ‘Insight into physics-based RRAM models – review’, J. Eng., 2019, 2019, (7), pp. 4644–4652.
11. 11)
  - 32. Chiu, F.-C.: ‘A review on conduction mechanisms in dielectric films’, Adv. Mater. Sci. Eng., 2014, 2014, pp. 1–18.
12. 12)
  - 13. Potteiger, T., Robinson, W.H.: ‘A one Zener diode, one memristor crossbar architecture for a write-time-based PUF’. Midwest Symp. Circuits Syst., Fort Collins, CO, 2015, pp. 1–4.
13. 13)
  - 17. Woo, J., Lee, D., Cha, E., et al: ‘Multilayer-oxide-based bidirectional cell selector device for cross-point resistive memory applications’, Appl. Phys. Lett., 2013, 103, (20), p. 202113.
14. 14)
  - 39. Jagath, A.L., Kumar, T.N., Almurib, H.A.F.: ‘Electrical model of Ta2O5/TaOx RRAM device with current conduction beyond RESET phase’. 2019 IEEE 9th Int. Nanoelectronics Conf. (INEC), Kuching, Malaysia, 2019, pp. 1–5.
15. 15)
  - 22. Saremi, M.: ‘Modeling and Simulation of the Programmable Metallization Cells (PMCs) and Diamond-Based Power Devices’, (2015) PhD Thesis, Arizona State University, 2017.
16. 16)
  - 29. Sze, S.M.: ‘Physics of semiconductor devices’ (Wiley Interscience, Hoboken, New Jersey, 1981, 2nd edn.).
17. 17)
  - 42. Zhang, L., Cosemans, S., Wouters, D.J., et al: ‘One-selector one-resistor cross-point array with threshold switching selector’, IEEE Trans. Electron Devices, 2015, 62, (10), pp. 3250–3257.
18. 18)
  - 23. Jo, S.H., Kumar, T., Narayanan, S., et al: ‘Cross-point resistive RAM based on field-assisted superliner threshold selector’, IEEE Trans. Electron Devices, 2015, 62, (11), pp. 3477–3481.
19. 19)
  - 11. Choi, B.J., Zhang, J., Norris, K., et al: ‘Trilayer tunnel selectors for memristor memory cells’, IEEE Electron Device Lett., 2016, 28, (5), pp. 261–267.
20. 20)
  - 34. Gehring, A., Selberherr, S.: ‘Gate current modeling for MOSFETs’, J. Comput. Theor. Nanosci., 2005, 2, pp. 26–44.
21. 21)
  - 26. Chen, A.: ‘A highly efficient and scalable model for crossbar arrays with non-linear selectors’. 2018 IEEE Int. Electron Devices Meeting (IEDM), San Francisco, CA, 2018, pp. 37.2.1–37.2.4.
22. 22)
  - 24. Huang, J., Tseng, Y.-M., Luo, W.-C., et al: ‘One selector-one resistor (1S1R) crossbar array for high-density flexible memory applications’. 2011 Int. Electron Devices Meeting, Washington, DC, 2011, pp. 31.7.1–31.7.4.
23. 23)
  - 35. Simmons, J.G.: ‘Electric tunnel effect between dissimilar electrodes separated by a thin insulating film’, J. Appl. Phys., 1963, 34, (9), pp. 2581–2590.
24. 24)
  - 1. Hatem, F.O., Ho, P.W.C., Kumar, T.N., et al: ‘Modeling of bipolar resistive switching of a non-linear MISM memristor’, Semicond. Sci. Technol., 2015, 30, (11), p. 115009.
25. 25)
  - 40. Chee, H.L., Kumar, T.N., Almurib, H.A.F.: ‘Electrical model of multi-level bipolar Ta2O5/TaOx bi-layered ReRAM’, Microelectron. J., 2019, 93, p. 104616.
26. 26)
  - 38. Hur, J.H., Lee, M.J., Lee, C.B., et al: ‘Modeling for bipolar resistive memory switching in transition-metal oxides’, Phys. Rev. B - Condens. Matter Mater. Phys., 2010, 82, (15), pp. 1–5.
27. 27)
  - 28. Jagath, A.L., Kumar, T.N., Almurib, H.A.F.: ‘Modelling of current conduction during RESET phase of Pt/Ta2O5/TaOx/Pt bipolar resistive RAM devices’. 2018 IEEE 7th Non-Volatile Memory Systems and Applications Symp. (NVMSA), Hakodate, Japan, 2018, pp. 55–60.
28. 28)
  - 20. Casperson, J.D., Bell, L.D., Atwater, H.A.: ‘Materials issues for layered tunnel barrier structures’, J. Appl. Phys., 2002, 92, (1), pp. 261–267.
29. 29)
  - 30. Southwick, R.G., Knowlton, W.B.: ‘Stacked dual-oxide MOS energy band diagram visual representation program (IRW student paper)’, IEEE Trans. Device Mater. Reliab., 2006, 6, (2), pp. 136–145.
30. 30)
  - 36. Ranuárez, J.C., Deen, M.J., Chen, C.-H.: ‘A review of gate tunneling current in MOS devices’, Microelectron. Reliab., 2006, 46, (12), pp. 1939–1956.
31. 31)
  - 3. Jiang, Z., Wu, Y., Yu, S., et al: ‘A compact model for metal – oxide resistive experiment verification’, IEEE Trans. Electron Devices, 2016, 63, (5), pp. 1–9.
32. 32)
  - 15. Yakopcic, C., Taha, T.M., Subramanyam, G., et al: ‘Analysis of a memristor based 1T1M crossbar architecture’. The 2011 Int. Joint Conf. on Neural Networks’, San Jose, CA, 2011, pp. 3243–3247.
33. 33)
  - 44. Chen, P., Yu, S.: ‘Compact modeling of RRAM devices and its applications in 1T1R and 1S1R array design’, IEEE Trans. Electron Devices, 2015, 62, (12), pp. 4022–4028.
34. 34)
  - 27. Woo, J., Peng, X., Yu, S.: ‘Design considerations of selector device in cross-point RRAM array for neuromorphic computing’. 2018 IEEE Int. Symp. on Circuits and Systems (ISCAS), Florence, 2018, pp. 1–4.
35. 35)
  - 18. Lee, W., Park, J., Kim, S., et al: ‘High current density and non-linearity combination of selection device based on TaOx/TiO2/TaOx structure for one selector-one resistor arrays’, ACS Nano, 2012, 6, (9), pp. 8166–8171.
36. 36)
  - 9. Bhattacharjee, D., Siemon, A., Linn, E., et al: ‘Efficient complementary resistive switch-based crossbar array booth multiplier’, Microelectron. J., 2017, 64, (March), pp. 78–85.
37. 37)
  - 12. Chen, A.: ‘Memory selector devices and crossbar array design: a modeling-based assessment’, J. Comput. Electron., 2017, 16, pp. 1186–1200.
38. 38)
  - 31. Govoreanu, B., Blomme, P., Rosmeulen, M., et al: ‘VARIOT: a novel multi-layer tunnel barrier concept for low-voltage nonvolatile memory devices’, IEEE Electron Device Lett., 2003, 24, (2), pp. 99–101.
39. 39)
  - 21. Wang, M., Zhou, J., Yang, Y., et al: ‘Conduction mechanism of a TaOx-based selector and its application in crossbar memory arrays’, Nanoscale, 2015, 7, (11), pp. 4964–4970.
40. 40)
  - 33. Micheloni, R., Marelli, A., Eshghi, K.: ‘Inside solid-state drives (SSDs)’ (Springer, New York, 2018).
41. 41)
  - 14. Tran, X.A., Yu, H.Y., Yeo, Y.C., et al: ‘A high-yield -based unipolar resistive RAM employing Ni electrode compatible with Si-diode selector for crossbar integration’, IEEE Electron Device Lett., 2011, 32, (3), pp. 396–398.
42. 42)
  - 41. Zhang, L., Cosemans, S., Wouters, D.J., et al: ‘Selector design considerations and requirements for 1 SIR RRAM crossbar array’. 2014 IEEE 6th Int. Memory Workshop (IMW), Taipei, 2014, pp. 1–4.
43. 43)
  - 19. Likharev, K.K.: ‘Layered tunnel barriers for nonvolatile memory devices’, Appl. Phys. Lett., 1998, 73, (15), pp. 2137–2139.
44. 44)
  - 37. Southwick, R.G., Sup, A., Jain, A., et al: ‘An interactive simulation tool for Complex multi-layer dielectric devices’, IEEE Trans. Device Mater. Reliab., 2011, 11, (2), pp. 236–243.
45. 45)
  - 16. Niu, G., Kim, H.-D., Roelofs, R., et al: ‘Material insights of HfO2-based integrated 1-transistor-1-resistor resistive random-access memory devices processed by batch atomic layer deposition’, Nat. Publ. Gr., 2016, 6, pp. 1–11.

Analytical modelling of tantalum/titanium oxide-based multi-layer selector to eliminate sneak path current in RRAM arrays

References

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