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access icon free Low storage power and high noise margin ternary memory cells in nanoelectronics

In recent years, due to the high ability of the multi-valued logic design in nanotechnology, the interest in the design of it has been renewed. Using multi-valued logic can lead to reduction of interconnections in the chip. This study presents two novel designs of a ternary memory cell using carbon nanotube field effect transistors (CNFETs) with only one supply voltage. In the previous works, a ternary latch has been used to store the ternary value, which has a considerably more static power and lower static noise margin in comparison to a binary latch. The proposed memory cells are based on decoding the ternary value to the binary one and saving in two binary latches; in this way, the storage power is sharply decreased and the static noise margin of the proposed ternary memory cell is also increased considerably to get close to that of a binary memory cell. The results of the simulation, using the HSPICE software and the Stanford 32 nm CNFET library with the voltage of 0.9 V, demonstrated that the proposed ternary memory cell achieved significant power saving and static noise margin improvement, as compared to the previous works with the same transistor count, which was expected.

References

    1. 1)
      • 5. Rezaei Khezeli, M., Moaiyeri, M.H., Jalali, A.: ‘Comparative analysis of simultaneous switching noise effects in MWCNT bundle and Cu power interconnects in CNTFET-based ternary circuits’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2019, 27, pp. 3746, https://doi.org/10.1109/TVLSI.2018.2869761.
    2. 2)
      • 19. Hosseini, S.A., Etezadi, S.: ‘A novel very low-complexity multi-valued logic comparator in nanoelectronics’, Circuits Syst. Signal Process., 2020, 39, pp. 223244, https://doi.org/10.1007/s00034-019-01158-2.
    3. 3)
      • 31. Moaiyri, M.H., Akbari, H., Moghaddam, M.: ‘An ultra-low-power and robust ternary static random access memory cell based on carbon nanotube FETs’, J. Nanoelectron. Optoelectron., 2018, 13, (4), pp. 617627.
    4. 4)
      • 26. Shahrom, E., Hosseini, S.A.: ‘A new low power multiplexer based ternary multiplier using CNTFETs’, AEU Int. J. Electron. Commun., 2018, 93, pp. 191207.
    5. 5)
      • 29. Cho, G., Lombardi, F.: ‘Design and process variation analysis of CNTFET-based ternary memory cells’, Integr. VLSI J., 2016, 54, pp. 97108.
    6. 6)
      • 15. Shahangian, M., Hosseini, S.A., Faghih Mirzaee, R.: ‘A universal method for designing multi-digit ternary-to-binary converter using CNTFET’, J. Circuits Syst. Comput., 2020, 29, (12), pp. 2050196-12050196-23, https://doi.org/10.11142/s02018-126-620501960.
    7. 7)
      • 22. Moaiyeri, M.H., Doostaregan, A., Navi, K.: ‘Design of energy-efficient and robust ternary circuits for nanotechnology’, IET Circuits Devices Syst., 2011, 5, (4), pp. 285296.
    8. 8)
      • 10. Rahman, A., Guo, J., Datta, S., et al: ‘Theory of ballistic nanotransistors’, IEEE Trans. Electron Devices, 2003, 50, (10), pp. 18531864.
    9. 9)
      • 34. Moghaddam, M., Timarchi, S., Moaiyeri, M.H., et al: ‘An ultra-low-power 9 T SRAM cell based on threshold voltage techniques’, Circuits Syst. Signal Process., 2016, 35, pp. 14371455.
    10. 10)
      • 8. Appenzeller, J.: ‘Carbon nanotubes for high-performance electronics progress and prospect’, Proc. IEEE, 2008, 96, (2), pp. 201211.
    11. 11)
      • 23. Moaiyeri, M.H., Mirzaee, R.F., Doostaregan, A., et al: ‘A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits’, IET Comput. Digit. Tech., 2013, 7, (4), pp. 167181.
    12. 12)
      • 35. Shreya, S., Sourav, S.: ‘Design, analysis and comparison between CNTFET based ternary SRAM cell and PCRAM cell’. Int. Conf. on Communication, Control and Intelligent Systems (CCIS), GLA University Mathura, India, 2015.
    13. 13)
      • 38. Stanford University CNFET model Website. Stanford University, Stanford, CA [Online], 2008. Available at http://nano.stanford.edu/model.php?Id=23.
    14. 14)
      • 12. Lin, Y., Appenzeller, J., Knoch, J., et al: ‘High-performance carbon nanotube field-effect transistor with tunable polarities’, IEEE Trans. Nanotechnol., 2005, 4, (5), pp. 481489.
    15. 15)
      • 1. Mukaidono, M.: ‘Regular ternary logic functions – ternary logic functions suitable for treating ambiguity’, IEEE Trans. Comput., 1986, 35, (2), pp. 179183.
    16. 16)
      • 32. You, K., Nepal, K.: ‘Design of a ternary static memory cell using carbon nanotube based transistors’, Micro Nano Lett., 2011, 6, (6), pp. 381385.
    17. 17)
      • 18. Sharifi, F., Panahi, A., Moaiyeri, M.H., et al: ‘High performance CNFET-based ternary full adders’, IETE J. Res., 2017, 64, (1), pp. 108115.
    18. 18)
      • 6. Balla, P.C., Antoniou, A.: ‘Low power dissipation MOS ternary logic family’, IEEE J. Solid-State Circuits, 1984, 19, (5), pp. 739749.
    19. 19)
      • 20. Lin, S., Kim, Y.B., Lombardi, F.: ‘The CNTFET-based design of ternary logic gates and arithmetic circuits’, IEEE Trans. Nanotechnol., 2011, 10, (2), pp. 217225.
    20. 20)
      • 28. Rahbari, K., Hosseini, S.A.: ‘Novel ternary D-flip-flap-flop and counter based on successor and predecessor in nanotechnology’, AEU Int. J. Electron. Commun., 2019, 109, pp. 107120.
    21. 21)
      • 24. Daraei, A., Hosseini, S.A.: ‘Novel energy-efficient and high-noise margin quaternary circuits in nanoelectronics’, AEU Int. J. Electron. Commun., 2019, 105, pp. 145162.
    22. 22)
      • 14. Shahangian, M., Hosseini, S.A., Pishgar Komleh, S.H.: ‘Design of a multi-digit binary-to-ternary converter based on CNTFETs’, Circuits Syst. Signal Process., 2019, 38, (6), pp. 25442563.
    23. 23)
      • 36. Singh, A., Singh Yadav, S., Kumar Singh, S., et al: ‘An overview of challenges in low power SRAM design’, Int. J. Electr. Electron. Comput. Sci. Eng., 2015, 2, (3), pp. 7477.
    24. 24)
      • 25. Roosta, E., Hosseini, S.A.: ‘A novel multiplexer-based quaternary full adder in nanoelectronics’, Circuits Syst. Signal Process., 2019, 38, pp. 40564078, https://doi.org/10.1007/s00034-019-01039-8.
    25. 25)
      • 27. Sridharan, K., Gurindagunta, S., Pudi, V.: ‘Efficient multiternary digit adder design in CNTFET technology’, IEEE Trans. Nanotechnol., 2013, 12, (3), pp. 283287.
    26. 26)
      • 17. Firouzi, S., Tabrizchi, S., Sharifi, F., et al: ‘High performance, variation-tolerant CNFET ternary full adder a process, voltage, and temperature variation-resilient design’, Comput. Electr. Eng., 2019, 77, pp. 205216.
    27. 27)
      • 2. Heung, A., Mouftah, H.T.: ‘Depletion/enhancement CMOS for a lower power family of three-valued logic circuits’, IEEE J. Solid-State Circuits, 1985, 20, (2), pp. 609616.
    28. 28)
      • 37. Takbiri, M., Faghih Mirzaee, R., Navi, K.: ‘Analytical review of noise margin in MVL: clarifcation of a deceptive matter’, Circuits Syst. Signal Process., 2019, 38, pp. 42804301.
    29. 29)
      • 33. Sayyah Ensan, S., Moaiyeri, M.H., Hessabi, S.: ‘A robust and low-power near-threshold SRAM in 10 nm FinFET technology’, Analog Integr. Circuits Signal Process., 2018, 94, (3), pp. 497506.
    30. 30)
      • 3. Moaiyeri, M.H., Taheri, Z.M., Khezeli, M.R., et al: ‘Efficient passive shielding of MWCNT interconnects to reduce crosstalk effects in multiple-valued logic circuits’, IEEE Trans. Electromagn. Compat., 2019, 61, pp. 15931601, https://doi.org/10.1109/TEMC.2018.2863378.
    31. 31)
      • 11. Tans, S.J., Verschueren, A.R.M., Dekker, C.: ‘Room-temperature transistor based on a single carbon nanotube’, Nature, 1998, 393, (7), pp. 4952.
    32. 32)
      • 7. Akturk, A., Pennington, G., Goldsman, N., et al: ‘Electron transport and velocity oscillations in a carbon nanotube’, IEEE Trans. Nanotechnol., 2007, 6, (4), pp. 469474.
    33. 33)
      • 16. Ghelichkhan, M., Hosseini, S.A., Pishgar Komleh, S.H.: ‘Multi-digit binary-to-quaternary and quaternary-to-binary converters and their applications in nanoelectronics’, Circuits Syst. Signal Process., 2020, 39, pp. 19201942, https://doi.org/10.1007/s00034-019-01235-6.
    34. 34)
      • 21. Etezadi, S., Hosseini, S.A.: ‘Novel ternary logic gates design in nanoelectronics’, AEEE Adv. Electr. Electron. Eng., 2019, 17, (3), pp. 294305.
    35. 35)
      • 4. Khezeli, M.R., Hossein Moaiyeri, M., Jalali, A.: ‘Active shielding of MWCNT bundle interconnects: an Efficient approach to cancellation of crosstalk-induced functional failures in ternary logic’, IEEE Trans. Electromagn. Compat., 2019, 61, pp. 100110, https://doi.org/10.1109/TEMC.2017.2788500.
    36. 36)
      • 13. Raychowdhury, A., Roy, K.: ‘Carbon-nanotube-based voltage-mode multiple-valued logic design’, IEEE Trans. Nanotechnol., 2005, 4, (2), pp. 168179.
    37. 37)
      • 9. Batchtold, A., Hadley, P., Nakanishi, T., et al: ‘Logic circuits with carbon nanotube transistors’, Science, 2001, 294, (9), pp. 13171320.
    38. 38)
      • 30. Lin, S., Kim, Y., Lombardi, F.: ‘Design of a ternary memory cell using CNTFETs’, IEEE Trans. Nanotechnol., 2012, 11, (5), pp. 10191025.
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