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access icon free Temperature sensitivity analysis of SGO metal strip JL TFET

Temperature sensitivity is one of the major concern in conventional stacked gate-oxide junctionless tunnel-field-effect transistor (SGO-JL-TFET). In this regard, the authors have investigated the sensitivity toward the temperature variation of the SGO-JL double-gate TFET with low work-function live strip (LWLS-SGO-JL-TFET) and without LWLS-SGO-JL-TFET (SGO-JL-TFET). Furthermore, they have analysed and compared the impact of operating temperature variation on the DC, analogue/radiofrequency and linearity performances of both the devices with the help of simulation results obtained using technology computer-aided design tool. It can be stated that the proposed device is less sensitive toward the temperature variation in terms of carrier concentration, electric field, on-state current and off-state current, as compared with conventional SGO-JL-TFET. Apart from these parameters, proposed device also demonstrates better temperature sensitivity in terms of analogue performance parameters such as transconductance cut-off frequency , gain bandwidth product and maximum oscillating frequency . Therefore, the proposed device can be a potential candidate for cryogenics and high-temperature applications.

References

    1. 1)
      • 3. Lu, W., Lieber, C.M.: ‘Semiconductor nanowires’, J. Phys. D, Appl. Phys., 2006, 39, (21), pp. R387R406.
    2. 2)
      • 28. Madan, J., Chaujar, R.: ‘Interfacial charge analysis of heterogeneous gate dielectric-gate all around-tunnel FET for improved device reliability’, IEEE Trans. Device Mater. Reliab., 2016, 16, (2), pp. 227234.
    3. 3)
      • 2. Cui, Y., Zhong, Z., Wang, D., et al: ‘High-performance silicon nanowire field-effect transistors’, Nano Lett., 2003, 3, (2), pp. 149152.
    4. 4)
      • 8. Avci, U.E., Morris, D.H., Young, I.A.: ‘Tunnel-field-effect transistors: prospects and challenges’, IEEE J. Electron Devices Soc., 2015, 3, (3), pp. 8895.
    5. 5)
      • 4. Gupta, S., Nigam, K., Pandey, S., et al: ‘Effect of interface trap charges on performance variation of heterogeneous gate dielectric junctionless TFET’, IEEE Trans. Electron Devices, 2017, 64, (11), pp. 47314737.
    6. 6)
      • 25. Lin, R., Lu, Q., Ranade, P., et al: ‘An adjustable work-function technology using Mo gate for CMOS devices’, IEEE Electron Device Lett., 2002, 23, (1), pp. 4951.
    7. 7)
      • 18. Lee, G., Jang, J.S., Choi, W.Y.: ‘Dual-dielectric-constant spacer hetero-gate-dielectric tunneling field-effect transistors’, Semicond. Sci. Technol., 2013, 28, (5), pp. 052001052005.
    8. 8)
      • 10. Kumar, S., Singh, K.S., Nigam, K., et al: ‘Dual-material dual-oxide double-gate TFET for improvement in DC characteristics, analog/RF and linearity performance’, Appl. Phys. A, 2019, 125, (5), pp. 353360.
    9. 9)
      • 20. Chiang, M.H., Lin, J.N., Kim, K., et al: ‘Random dopant fluctuation in limited-width FinFET technologies’, IEEE Trans. Electron Devices, 2007, 54, (8), pp. 20552060.
    10. 10)
      • 7. Seabaugh, A.C., Zhang, Q.: ‘Low-voltage tunnel transistors for beyond CMOS logic’, Proc. IEEE, 2010, 98, (12), pp. 20952110.
    11. 11)
      • 23. Yadav, S., Madhukar, R., Sharma, D., et al: ‘A new structure of electrically doped TFET for improving electronic characteristics’, Appl. Phys. A, 2018, 124, (7), pp. 517526.
    12. 12)
      • 34. Nigam, K., Kondekar, P., Sharma, D.: ‘DC characteristics and analog/RF performance of novel polarity control GaAs–Ge-based tunnel-field-effect transistor’, Superlattices Microstruct., 2016, 92, pp. 224231.
    13. 13)
      • 26. Venkatesh, P., Nigam, K., Pandey, S., et al: ‘Impact of interface trap charges on performance of electrically doped tunnel FET with heterogeneous gate dielectric’, IEEE Trans. Device Mater. Reliab., 2017, 17, (1), pp. 245252.
    14. 14)
      • 12. Nayfeh, O., Chleirigh, C., Hennessy, J.: ‘Design of tunneling field-effect transistors using strained silicon/strained germanium type-II staggered heterojunctions’, IEEE Electron Device Lett., 2008, 29, (9), pp. 10741077.
    15. 15)
      • 36. Chandan, B.V., Nigam, K., Pandey, S., et al: ‘Temperature sensitivity analysis on analog/RF and linearity metrics of electrically doped tunnel FET’. Conf. Information and Communication Technology, Gwalior, India, 2017, pp. 15.
    16. 16)
      • 9. Esseni, D., Guglielmini, M., Kapidani, B., et al: ‘Tunnel FETs for ultra-low-voltage digital VLSI circuits: part I – device-circuit interaction and evaluation at device level’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2014, 22, (12), pp. 24882498.
    17. 17)
      • 17. Cui, N., Liang, R., Xua, J.: ‘Heteromaterial gate tunnel-field-effect transistor with lateral energy band profile modulation’, Appl. Phys. Lett., 2011, 98, pp. 142105-1142105-3.
    18. 18)
      • 15. Jhaveri, R., Nagavarapu, N.V., Woo, J.C.S.: ‘Effect of pocket doping and annealing schemes on the source-pocket tunnel-field-effect transistor’, IEEE Trans. Electron Devices, 2011, 58, (1), pp. 8086.
    19. 19)
      • 1. Yan, R.H., Abbas, O., Lee, K.F.: ‘Scaling the Si MOSFET: from bulk to SOI to bulk’, IEEE Trans. Electron Devices, 1992, 39, (7), pp. 17041710.
    20. 20)
      • 24. Yadav, S., Lemtur, A., Sharma, D., et al: ‘Effective approach to enhance DC and high-frequency performance of electrically doped TFET’, Micro & Nano Lett.,2018, 13, (10), pp. 14691474.
    21. 21)
      • 11. Saurabh, S., Kumar, M.J.: ‘Impact of strain on drain current and threshold voltage of nanoscale double-gate tunnel-field-effect transistor: theoretical investigation and analysis’, Jpn. J. Appl. Phys., 2009, 48, p.064503.
    22. 22)
      • 5. Boucart, K., Ionescu, A.M.: ‘Double-gate tunnel FET with high-k gate dielectric’, IEEE Trans. Electron Devices, 2007, 54, (7), pp. 17251733.
    23. 23)
      • 13. Mohata, D., Mookerjea, S., Agrawal, A.: ‘Experimental staggered source and N+ pocket-doped channel III–V tunnel-field-effect transistors and their scalabilities’, Appl. Phys. Express, 2011, 4, (2), pp. 024105024107.
    24. 24)
      • 22. Bhardwaj, E., Nigam, K., Chaturvedi, S., et al: ‘Effect of ITCs on gate stacked JL-TFET based on work-function engineering’, Micro & Nano Lett., 2019, 14, (12), pp. 12381243.
    25. 25)
      • 21. Nigam, K., Kondekar, P., Sharma, D., et al: ‘A new approach for design and investigation of junctionless tunnel FET using electrically doped mechanism’, Superlattices Microstruct., 2016, 98, pp. 17.
    26. 26)
      • 35. Shrivastava, V., Kumar, A., Sahu, C., et al: ‘Temperature sensitivity analysis of dopingless charge-plasma transistor’, Solid-State Electron., 2016, 117, pp. 9499.
    27. 27)
      • 19. Lee, M.J., Choi, W.Y.: ‘Effects of device geometry on hetero-gate-dielectric tunneling field-effect transistors’, IEEE Electron Device Lett., 2012, 33, (10), pp. 14591461.
    28. 28)
      • 27. Ghosh, P., Bhowmick, B.: ‘Effect of temperature on reliability issues of ferroelectric dopant segregated Schottky barrier tunnel-field-effect transistor (Fe DS-SBTFET)’, Silicon, 2019, 12, (53), pp. 18.
    29. 29)
      • 16. Chang, H., Adams, B., Chien, P., et al: ‘Improved subthreshold and output characteristics of source-pocket Si tunnel FET by the application of laser annealing’, IEEE Trans. Electron Devices, 2013, 60, (1), pp. 9296.
    30. 30)
      • 30. Ghosh, P., Haldar, S., Gupta, R.S., et al: ‘An investigation of linearity performance and intermodulation distortion of GME CGT MOSFET for RFIC design’, IEEE Trans. Electron Devices, 2012, 59, (12), pp. 32633268.
    31. 31)
      • 29. Ghosh, B., Akram, M.W.: ‘Junctionless tunnel-field-effect transistor’, IEEE Electron Device Lett., 2013, 34, (5), pp. 584586.
    32. 32)
      • 32. Ward, D.E., Dutton, R.W.: ‘A charge oriented model for MOS transistor capacitances’, IEEE J. Solid-State Circ., 1978, 13, (5), pp. 703708.
    33. 33)
      • 14. Cao, W., Yao, C.J., Jiao, G.F.: ‘Improvement in reliability of tunneling field-effect transistor with p–n–i–n structure’, IEEE Trans. Electron Devices, 2011, 58, (7), pp. 21222126.
    34. 34)
      • 33. Nigam, K., Pandey, S., Kondekar, P.N., et al: ‘Temperature sensitivity analysis of polarity controlled electrostatically doped tunnel-field-effect transistor’, Superlattices Microstruct., 2016, 97, pp. 598605.
    35. 35)
      • 37. Sarkar, A., Das, A.K., De, S., et al: ‘Effect of gate engineering in double-gate MOSFETs for analog/RF applications’, Microelectron. J., 2012, 43, (11), pp. 873882.
    36. 36)
      • 6. Kim, S.W., Kim, J.H., Liu, T.J.K., et al: ‘Demonstration of L-shaped tunnel-field-effect transistors’, IEEE Trans. Electron Devices, 2016, 63, (4), pp. 17741778.
    37. 37)
      • 31. Nigam, K., Pandey, S., Kondekar, P.N., et al: ‘Temperature sensitivity analysis of polarity controlled electrostatically doped hetero-TFET’. 12th Conf. Microelectronics and Electronics (PRIME), Lisbon, Portugal, 2016, pp. 14.
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