This work presents techniques that effectively utilise comparator timing information to accelerate low-voltage successive approximation register (SAR) analogue-to-digital converter (ADC) operation. Compared to existing approaches that only exploit the prolonged comparator decision time in the events of metastability, the proposed techniques are effective in a broader voltage range and can extract more information about the voltages being compared. To cope with large variations associated with comparator delay, this work proposes robust timing measurement circuit, uncertainty-tolerant search algorithm and circuit adaptive tuning techniques. The adaptive tuning technique enables ADC to autonomously find voltage levels corresponding to the outputs of the timing measurement circuit as well as to adjust the uncertainty ranges used in the search algorithm. This eliminates the need of post-silicon calibration for the timing measurement circuits, which are typically required in existing approaches. The developed techniques are used in the design of a 9-bit 0.45 V SAR ADC circuit with a 130 nm complementary metal–oxide–semiconductor technology. Measurement results from the prototype chip indicate that for most input levels the proposed ADC completes conversion in six or seven conversion cycles. At 200 KS/s sampling rate, its power dissipation is 2.88 µW and it achieves a signal-to-noise distortion ratio of 50.66 dB with a figure of merit of 51.8 fJ/c.-s.