access icon free Sizing of the CMOS 6T-SRAM cell for NBTI ageing mitigation

This study presents a negative bias temperature instability (NBTI) mitigation design technique for CMOS 6T-static random access memory (6T-SRAM) cells. The proposed approach is based on transistor sizing technique. It consists of sizing the nMOS access transistors of the cell to alleviate NBTI ageing occurring in its pMOS pull-up transistors threatening the cell stability. Once the access transistors are sized for a better hold static noise margin under NBTI, the other transistors of the 6T-SRAM cell could be properly sized for improved read stability and write-ability.

Inspec keywords: CMOS memory circuits; negative bias temperature instability; MOSFET circuits; SRAM chips; integrated circuit reliability

Other keywords: NBTI ageing mitigation; write-ability; cell stability; CMOS 6T-SRAM cell; read stability; transistor sizing technique; CMOS 6T-static random access memory cells; negative bias temperature instability mitigation; nMOS access transistors; pMOS pull-up transistors

Subjects: CMOS integrated circuits; Memory circuits; Semiconductor storage; Reliability

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