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High-speed and area-efficient scalable N-bit digital comparator

High-speed and area-efficient scalable N-bit digital comparator

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An area-efficient N-bit digital comparator with high operating speed and low-power dissipation is presented in this work. The proposed comparator structure consists of two separate modules. The first module is the comparison evaluation module (CEM) and the second module is the final module (FM). Independent from the input operand bitwidths, stages present in CEM involve the regular structure of repeated logic cells used for implementing parallel prefix tree structure. The FM validates the final comparison based on results obtained from the CEM. The presence of regular very large-scale integration topology in the proposed structure allows the analytical derivation of the area in terms of total number of transistors present in the design and total delay encountered in input–output flow as the function of input operand bitwidth. Spectre simulation results have been presented using 0.18 µm complementary metal–oxide–semiconductor (CMOS) technology at 1 GHz. The main advantages of the proposed comparator are minimum input–output delay of 0.57 ns, minimum fan-out-of-4 delay of 9.5 ns and low-power dissipation of 1.03 mw as compared with existing comparators designed using 180 nm CMOS technology for 64 bit comparison.

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