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Designers must carefully choose the bestsuited fast Fourier transform (FFT) algorithm among various available techniques for the custom implementation that meets their design requirements, such as throughput, latency, and area. This article, to the best of authors' knowledge, is the first to present a compact and yet highthroughput parameterisable hardware architecture for implementing different FFT algorithms, including radix2, radix4, radix8, mixedradix, and splitradix algorithms. The designed architectures are fully parameterisable to support a variety of transform lengths and variable wordlengths. The FFT algorithms have been modelled and simulated in doubleprecision floatingpoint and fixedpoint representations using authors' customdeveloped library of numerical operations. The designed FFT architectures are modelled in Verilog hardware description language and their cycleaccurate and bittrue simulation results are verified against their fixedpoint simulation models. The characteristics and implementation results of various FFT architectures on a Xilinx Virtex7 FPGA are presented. Compared to recently published works, authors' memorybased FFT architectures utilise less reconfigurable resources while maintaining comparable or higher operating frequencies. The ASIC implementation results in a standard 45nm CMOS technology are also presented for the designed memorybased FFT architectures. The execution times of FFTs on a workstation and a graphics processing unit are compared against authors' FPGA implementations.
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http://iet.metastore.ingenta.com/content/journals/10.1049/ietcds.2018.5556
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