access icon free Approach for low power high speed 4-bit flash analogue to digital converter

In this study a new structure was presented to design and simulate a considerably low power and high-speed 4-bit flash analogue to digital converter based on TSMC 0.18 µm complementary metal-oxide semiconductor (CMOS) technology. In this structure, in order to reduce the power consumption in the proposed comparator, the reference voltage was removed and replaced with the threshold voltage of CMOS transistors. This method has reduced the power consumption greatly. Additionally, by employing reversible logic in the 2:1 multiplier, the power consumption and the number of stages were dropped and obtaining a faster converter was considered as the other breakthrough. The simulation was carried out in 1.8 V supply voltage and power consumption of 330 µW while the sampling rate was equal to 2GSample/s.

Inspec keywords: low-power electronics; multiplying circuits; analogue-digital conversion; comparators (circuits); CMOS logic circuits

Other keywords: size 0.18 mum; CMOS transistors; reversible logic; CMOS technology; power 330.0 muW; low power flash analogue to digital converter; voltage 1.8 V; word length 4 bit; TSMC complementary metal-oxide semiconductor technology; comparator; high-speed flash analogue to digital converter; power consumption

Subjects: CMOS integrated circuits; A/D and D/A convertors; Logic circuits; A/D and D/A convertors; Electrical/electronic equipment (energy utilisation); Logic and switching circuits

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