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Approach for low power high speed 4-bit flash analogue to digital converter

Approach for low power high speed 4-bit flash analogue to digital converter

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In this study a new structure was presented to design and simulate a considerably low power and high-speed 4-bit flash analogue to digital converter based on TSMC 0.18 µm complementary metal-oxide semiconductor (CMOS) technology. In this structure, in order to reduce the power consumption in the proposed comparator, the reference voltage was removed and replaced with the threshold voltage of CMOS transistors. This method has reduced the power consumption greatly. Additionally, by employing reversible logic in the 2:1 multiplier, the power consumption and the number of stages were dropped and obtaining a faster converter was considered as the other breakthrough. The simulation was carried out in 1.8 V supply voltage and power consumption of 330 µW while the sampling rate was equal to 2GSample/s.

References

    1. 1)
      • 14. Zhang, S., Li, Z., Ling, B.: ‘Design of high-speed and low-power comparator in flash ADC’, Proc. Eng., 2012, 29, pp. 687692, Doi: 10.1016/j.proeng.2012.01.024.
    2. 2)
      • 2. Kim, D., Park, S., Lee, M, et al: ‘An 8-bit 2 GS/s 80 mW high accurate CMOS folding A/D converter with a symmetrical zero-crossing technique’, Analog Integr. Circuits Signal Process., 2016, 86, (3), pp. 407415, Doi: 10.1007/s10470-016-0693-5.
    3. 3)
      • 30. Mayur, S.M., Siddharth, R.K., Nithin Kumar, Y.B., et al: ‘Design of low power 4-bit 400MS/s standard cell based flash ADC’. IEEE Computer Society Annual Symp. on VLSI (ISVLSI), Bochum, Germany, 2017, pp. 600603.
    4. 4)
      • 6. Zahrai, S.A., Onabajo, M.: ‘Review of analog-to-digital conversion characteristics and design considerations for the creation of power-efficient hybrid data converters’, J. Low Power Electron. Appl., 2018, 8, p. 12, Doi: 10.3390/jlpea8020012.
    5. 5)
      • 22. Prudhvi Raj, K., Syamala, Y.: ‘Transistor level implementation of digital reversible circuits’, Int. J. VLSI Design Commun. Syst. (VLSICS), 2014, 5, (6), pp. 4361.
    6. 6)
      • 1. van de Plassche, R.: ‘CMOS integrated analog-to-digital and digital-to-analog converters’ (Kluwer Academic Publishers, Boston, 2003, 2nd edn.) DOI: 10.1007/978-1-4757-3768-4.
    7. 7)
      • 23. Raghavendra, R., Dr Hariprasad, S.A.: ‘Implementation of flash ADC using multisim technology’, Int. J. Comput. Trends Technol. (IJCTT), 2013, 4, (6), pp. 18251830, ISSN: 2231-2803.
    8. 8)
      • 13. Khorami, A., Sharifkhani, M.: ‘Excess power elimination in high-resolution dynamic comparators’, Microelectron. J., 2017, 64, pp. 4552, Doi: 10.1016/j.mejo.2017.04.006.
    9. 9)
      • 11. Deepika, V., Singh, S.: ‘Design and implementation of a low-power, high-speed comparator’, Proc. Mater. Sci., 2015, 10, pp. 314322, Doi: 10.1016/j.mspro.2015.06.06.
    10. 10)
      • 9. Singh, J.: ‘High speed multi-channel data acquisition chip’. IEEE Int. Conf. on Electronics, Circuits and Systems, Lisboa, Portugal, vol. 1, 1998, pp. 401404.
    11. 11)
      • 29. Rahul, P.V., Kulkarni, A.A., Sankanur, S., et al: ‘Reduced-comparators-for-low-power-flash-ADC-using-TSMC018’. Int. Conf. on Microelectronic Devices, Circuits and Systems (ICMDCS), Vellore, India, 2017, pp. 15.
    12. 12)
      • 31. Murugesh, H.M., Dr Nagesh, K.N., Satheesha, T.Y.: ‘Implementation of 4-BIT two step flash ADC using 180 nm technology’, Int. J. Technol. Res. Eng., 2016, 3, (10), pp. 29132916, ISSN (Online): 2347–4718.
    13. 13)
      • 16. Yoo, J., Choi, K., Tangel, A.: ‘A 1-GSPS CMOS flash A/D converter for system-on-chip applications’. IEEE Computer society workshop on VLSI 2001, Emerging Technologies for VLSI Systems, Orlando, FL, USA, pp. 135139, Doi: 10.1109/IWV.2001.923152.
    14. 14)
      • 21. Bennett, C.H.: ‘Logical reversibility of computation’, IBM J. Res. Dev., 1973, 17, (6), pp. 525532.
    15. 15)
      • 4. Tretter, G., Khafaji, M., Fritsche, D., et al: ‘A 24 GS/s single-core flash ADC with 3 bit resolution in 28 nm low-power digital CMOS’. Radio Frequency Integrated Circuits Symp. (RFIC), Phoenix, AZ, USA, 2015, pp. 347350.
    16. 16)
      • 7. Stojcevski, A., Le, H.P., Singh, J., et al: ‘Flash ADC architecture, IET Circuits, Devices Systems,Electron. Lett., 2003, 39, (6), pp. 501502, Doi: 10.1049/el:20030290.
    17. 17)
      • 15. Abumurad, A., Choi, K.: ‘Design procedure and selection of TIQ comparators for flash ADCs’, Circuits Syst. Signal Process., 2018, 37, (2), pp. 500531, Doi: 10.1007/s00034-017-0574-x.
    18. 18)
      • 34. Varghese, G.T., Mahapatra, K.: ‘A low power reconfigurable encoder for flash ADCs. Global Colloquium in recent advancement and effectual researches in engineering, science and technology (RAEREST 2016)’,Proc. Technol., 2016, 25, pp. 574581, Doi: 10.1016/j.protcy.2016.08.147.
    19. 19)
      • 26. Posch, W., Enichlmair, H., Schirgi, E., et al: ‘Statistical modelling of MOS transistor mismatch for high-voltage CMOS processes’, FnQuality Reliability Eng., 2005, 21, (5), pp. 477489, Doi: 10.1002/qre.735.
    20. 20)
      • 18. Aytar, O., Tangel, A.: ‘Employing threshold inverter quantization (TIQ) technique in designing 9-bit folding and interpolation CMOS analog-to-digital converters (ADC)’, Sci. Res. Essays, 2011, 6, (2), pp. 351362, Doi: 10.5897/SRE10.793.
    21. 21)
      • 10. Khorami, A., Sharifkhani, M.: ‘High-speed low-power comparator for analog to digital converters’, AEU-Int. J. Electron. Commun., 2016, 70, (7), pp. 886894, Doi: 10.1016/j.aeue.2016.04.002.
    22. 22)
      • 32. Torfs, G., Li, Z., Bauwelinck, J., et al: ‘Low-power 4-bit flash analogue to digital converter for ranging applications’, IET Circuits, Devices Syst., Electron. Lett., 2011, 47, (1), pp. 2022, DOI: 10.1049/el.2010.2213.
    23. 23)
      • 5. Yewale, S., Gamad, R.: ‘Design of low power and high speed MOS comparator for A/D converter application’, Wirel. Eng. Technol., 2012, 3, pp. 9095.
    24. 24)
      • 33. Kumre, L., Ramesh, N.V.: ‘Design and implementation of flash analog to digital converter’. 214-7853© 2017 Elsevier Ltd. All rights reserved, Selection and Peer-review under responsibility of International Conference on Processing of Materials, Minerals and Energy, (July 29th–30th) 2016, Ongole, Andhra Pradesh, India, Materials Today: Proceedings, Ongole, Andhra Pradesh, India, vol. 5, 2018, pp. 11041113.
    25. 25)
      • 19. Palsodkar, P., Dakhole, P., Palsodkar, P.: ‘Reduced complexity linearity improved threshold quantized comparator based flash ADC’, J. Circuits Syst. Comput., 2017, 26, (3), p. 1750046, Doi: 10.1142/S0218126617500463.
    26. 26)
      • 28. Thakur, K., Kingra, S.K.: ‘Design and implementation of hybrid 4-bit flash ADC’. Int. Conf. on Advances in Computing, Communications and Informatics (ICACCI), Jaipur, India, 2016, pp. 12331237.
    27. 27)
      • 17. Talukder, A.-A., Sarker, Md.S.: ‘A three-bit threshold inverter quantization based CMOS flash ADC’. 4th Int. Conf. on Advances in Electrical Engineering (ICAEE), 2017, 2017, pp. 352356, Doi: 10.1109/ICAEE.2017.8255380.
    28. 28)
      • 27. Kumar, S., Yadav, R.: ‘Design of 4-bit flash ADC using 180 nm technology’, Int. J. Sci. Res. Dev., 2017, 5, (4), pp. 11791181, ISSN (online): 2321-0613.
    29. 29)
      • 12. Hassanpourghadi, M., Zamani, M., Sharifkhani, M.: ‘A low-power low-offset dynamic comparator for analog to digital converters’, Microelectron. J., 2014, 45, (2), pp. 256262, Doi: 10.1016/j.mejo.2013.11.012.
    30. 30)
      • 20. Zhu, S., Wu, B., Cai, Y., et al: ‘A 2-GS/s 8-bit non-interleaved time-domain flash adc based on remainder number system in 65 nm CMOS’, IEEE J. Solid-State Circuits, 2018, 53, (4), pp. 11721183, Doi: 10.1109/JSSC.2017.2774280.
    31. 31)
      • 8. Kiran, K.R., Kumar, A., Reddy, A.S., et al: ‘A 5-bit, 0.08 mm 2 area flash analog to digital converter implemented on cadence virtuoso 180nm’. Int. Conf. Emerging Trends in Engineering, Technology and Science (ICETETS), Pudukkottai, India, 2016.
    32. 32)
      • 24. Onabajo, M., Silva-Martinez, J.: ‘Analog circuit design for process variation-resilient systems-on-a-chip’ (Springer-Verlag, New York, 2012), Doi: 10.1007/978-1-4614-2296-9.
    33. 33)
      • 25. Pelgrom, M.J.M., Duinmaijer, A.C.J., Welbers, A.P.G.: ‘Matching properties of MOS transistors’, IEEE J. Solid-State Circuits, 1989, 24, (5), pp. 14331439, Doi: 10.1109/JSSC.1989.572629.
    34. 34)
      • 3. Gustavsson, M., JacobWikner, J., Tan, N.N.: ‘CMOS data converters for communications’ (Kluwer Academic Publishers, USA, 2002).
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