Your browser does not support JavaScript!

Assessment of interface traps in In0.53Ga0.47As FinFET with gate-to-source/drain underlap for sub-14 nm technology node to impede short channel effect

Assessment of interface traps in In0.53Ga0.47As FinFET with gate-to-source/drain underlap for sub-14 nm technology node to impede short channel effect

For access to this article, please select a purchase option:

Buy article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
IET Circuits, Devices & Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Silicon fin field-effect transistor (FinFET) devices with gate–source/drain underlap fin length (L un) structures have been used for effective reduction in short channel effects (SCEs) from many years. Here, investigations have been performed on the FinFET structure with In0.53Ga0.47As material. Three-dimensional technology computer-aided design simulations for 14 nm channel length In0.53Ga0.47As FinFETs with underlap have been conducted by incorporating various effects to analyse the influence of interface traps on the device. The dominance of traps is investigated on SCE and intrinsic delay to assess the trend on underlap devices. The impact on threshold voltage and on current due to metal gate work function (MGWF) variation has been also demonstrated. Simulations have been carried out for L un = 0, 3, 6, and 9 nm with interface trap density of 1012 and 1014 cm–2 eV–1. Improvement in the subthreshold swing (SS) is observed as the L un increases but at the cost of intrinsic delay. However, the improvement in SS after L un = 6 nm is nearly constant. It has been also observed that the relative standard deviation of the threshold voltage and on current variation due to MGWF variation improves as the L un increases till 6 nm after that this improvement is not very significant.


    1. 1)
      • 12. Yang, J.W., Zeitzoff, P.M., Tseng, H.H.: ‘Highly manufacturable double-gate fin-FET with gate-source/drain underlap’, IEEE Trans. Electron Devices, 2007, 54, (6), pp. 14641470.
    2. 2)
      • 4. Xuan, Y., Wu, Y.Q., Ye, P.D.: ‘High performance inversion type enhancement-mode InGaAs MOSFET with maximum drain current exceeding 1 A/mm’, IEEE Electron Device Lett., 2008, 29, (4), pp. 294296.
    3. 3)
      • 5. Zhao, H., Yum, J.H., Chen, Y.T., et al: ‘In0.53Ga0.47As n-metal-oxide-semiconductor field effect transistors with atomic layer deposited Al2O3, HfO2, and LaAlO3 gate dielectrics’, J. Vac. Sci. Tech. B, Micro Nano Struct. Process. Meas. Phenom., 2009, 27, (4), pp. 20242027.
    4. 4)
      • 9. O'Connor, E., Long, R., Cherkaoui, K., et al: ‘In situ H2S passivation of In0.53Ga0.47As InP metal-oxide-semiconductor capacitors with atomic-layer deposited HfO2 gate dielectric’, Appl. Phys. Lett., 2008, 92, p. 022902.
    5. 5)
      • 23. Hurkx, G., De-Graaff, H., Kloosterman, W., et al: ‘A new analytical diode model including tunneling and avalanche breakdown’, IEEE Trans. Electron Devices, 1992, 39, (9), pp. 20902098.
    6. 6)
      • 7. Passlack, M., Zurcher, P., Rajagopalan, K., et al: ‘High mobility III-V MOSFETs for RF and digital applications’. Proc. Int. Electron Devices Meeting (IEDM), Washington, DC, USA, 2007, pp. 621624.
    7. 7)
      • 16. Seoane, N., Aldegunde, M., Garcı, A., et al: ‘3D atomistic simulations of dopant induced variability in nanoscale implant free In0.75Ga0.25As MOSFETs’, Solid-State Electron., 2012, 69, pp. 4349.
    8. 8)
      • 11. Das, R., Pandit, P., Chakraborty, S., et al: ‘An optimisation based study of underlap architecture of sub 16 nm double gate MOSFET for enhanced analog performance’, Mater. Focus, 2017, 6, (3), pp. 305309.
    9. 9)
      • 3. Koveshnikov, S., Goel, N., Majhi, P., et al: ‘In0.53Ga0.47As based metal oxide semiconductor capacitors with atomic layer deposition ZrO2 gate oxide demonstrating low gate leakage current and equivalent oxide thickness less than 1 nm’, Appl. Phys. Lett., 2008, 92, (22), p. 222904.
    10. 10)
      • 26. Synopsys Inc.: ‘Manual, sentaurus user's’ (Synopsys Inc., Mountain View, CA, 2016).
    11. 11)
      • 8. Ahn, J., McIntyre, P.C.: ‘Trimethylaluminum passivation of Al2O3/InGaAs interface for metal-oxide-semiconductor devices’. Meeting Abstracts, Seattle, Washington, 2012, pp. 774774.
    12. 12)
      • 10. Kim, T.W., Kwon, H.M., Shin, S.H., et al: ‘Impact of H2 high-pressure annealing onto InGaAs quantum-well metal-oxide-semiconductor field-effect transistors with Al2O3/HfO2 gate-stack’, IEEE Electron Device Lett., 2015, 36, (7), pp. 672674.
    13. 13)
      • 20. ITRS: ‘International Technology Roadmap for Semiconductors’, 2013. Available at
    14. 14)
      • 14. Li, Y., Hwang, C.H., Li, T.Y., et al: ‘Simulation of electrical characteristic fluctuation in 16-nm FinFET's and circuits’. Proc. Device Research Conf. (DRC), University Park, PA, USA, 2009, pp. 139140.
    15. 15)
      • 22. Hurkx, G., Klaassen, D., Knuvers, M.: ‘A new recombination model for device simulation including tunneling’, IEEE Trans. Electron Devices, 1992, 39, (2), pp. 331338.
    16. 16)
      • 21. Djara, V., Deshpande, V., Sousa, M., et al: ‘CMOS-compatible replacement metal gate InGaAs-OI FinFET with ION = 156 µA/µm at VDD = 0.5 V and IOFF = 100 nA/µm’, IEEE Electron Device Lett., 2016, 37, (2), pp. 169172.
    17. 17)
      • 15. Seoane, N., Indalecio, G., Aldegunde, M., et al: ‘Comparison of fin-edge roughness and metal grain work function variability in InGaAs and Si FinFETs’, IEEE Trans. Electron Devices, 2016, 63, (3), pp. 12091216.
    18. 18)
      • 2. Seoane, N., Aldegunde, M., Nagy, D., et al: ‘Simulation study of scaled In0.53Ga0.47As and Si FinFETs for sub-16 nm technology nodes’, Semi. Sci. Tech., 2016, 31, (7), pp. 7500575011.
    19. 19)
      • 18. Seoane, N., Indalecio, G., Comesana, E., et al: ‘Three-dimensional simulations of random dopant and metal-gate work-function variability in an In0.53Ga0.47As GAA MOSFET’, IEEE Electron Device Lett., 2013, 34, (2), pp. 205207.
    20. 20)
      • 6. Ajayan, J., Nirmal, D., Prajoon, P., et al: ‘Analysis of nanometer-scale InGaAs/InAs/InGaAs composite channel MOSFETs using high-K dielectrics for high speed applications’, AEU-Int. J. Electron. Commun., 2017, 79, pp. 151157.
    21. 21)
      • 1. Kalna, K., Seoane, N.: ‘Benchmarking of scaled InGaAs implant-free nanoMOSFETs’, IEEE Trans. Electron Devices, 2008, 55, (9), pp. 22972306.
    22. 22)
      • 19. Seoane, N., Indalecio, G., Comesana, E., et al: ‘Random dopant, line-edge roughness, and gate workfunction variability in a nano InGaAs FinFET’, IEEE Trans. Electron Devices, 2014, 61, (2), pp. 466472.
    23. 23)
      • 17. Asenov, A., Kaya, S., Brown, A.R.: ‘Intrinsic parameter fluctuations in decananometer MOSFETS introduced by gate line edge roughness’, IEEE Trans. Electron Devices, 2003, 50, (5), pp. 12541260.
    24. 24)
      • 13. Trivedi, V., Fossum, J.G., Chowdhury, M.M.: ‘Nanoscale FinFETs with gate-source/drain underlap’, IEEE Trans. Electron Devices, 2005, 52, (1), pp. 5662.
    25. 25)
      • 25. Lin, J., Lee, S., Oh, H.J., et al: ‘Plasma PH3-passivated high mobility inversion InGaAs MOSFET fabricated with self-aligned gate-first process and HfO2/TaN gate stack’. Proc. Int. Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2008, pp. 14.
    26. 26)
      • 24. Pathak, J., Darji, A.: ‘Investigation of TCADs models for characterization of sub 16 nm In0.53Ga0.47As FinFET’. Int. Symp. on VLSI Design and Test, IIT Roorkee, India, 2017, pp. 279286.

Related content

This is a required field
Please enter a valid email address