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access icon free Analytical modelling of dielectric engineered strained dual-material double-gate-tunnelling field effect transistor

© The Institution of Engineering and Technology
Received 23/06/2018, Accepted 06/06/2019, Revised 16/04/2019, Published 11/06/2019

In this endeavour, the fruition of a resurrected tunnel field effect transistor has been investigated incorporating the idea of strained channel engineering along with the implementation of dielectric modulation technique. A non-homogeneous pattern of gate oxide layer is considered with hetero-dielectric architecture at the front gate and linearly graded oxide at the back gate. The buried oxide (BOX) thickness is kept intentionally double that of front oxide one to reduce electric field lines penetrating from drain to source, thus minimising fringing field effect. The surface potential function has been deduced with the help of 2D Poisson's equation assuming appropriate boundary conditions. Lateral electric field and hence total electric field have been computed from channel potential to study tunnelling efficiency, hot carrier effect and drain induced barrier lowering for the aimed device. Finally drain current has been derived with the help of Kane's model upon integration of band-to-band tunnelling rate and the results have been compared with previously published reports to corroborate the eminence of the proposed model. All analytical corollaries are in adroit amity with Silvaco ATLAS simulated data for avowal of the developed modelin terms of sublime short channel behaviour.

Inspec keywords: surface potential; tunnel field-effect transistors; electric fields; hot carriers; semiconductor device models; Poisson equation

Other keywords: Silvaco ATLAS; hot carrier effect; 2D Poisson equation; electric field lines; drain induced barrier; nonhomogeneous pattern; dielectric modulation technique; strained channel engineering; surface potential function; fringing field effect; buried oxide thickness; band-to-band tunnelling rate; dielectric engineered strained dual-material; dual-material double-gate-tunnelling field effect transistor; channel potential; total electric field; resurrected tunnel field effect transistor; lateral electric field; Kane model; gate oxide layer; hetero-dielectric architecture

Subjects: Differential equations (numerical analysis); Other field effect devices; Semiconductor device modelling, equivalent circuits, design and testing

References

    1. 1)
      • 19. Upasana, N.R., Saxena, M., Gupta, M.: ‘Modeling and TCAD assessment for gate material and gate dielectric engineered TFET architectures: circuit-level investigation for digital applications’, IEEE Trans. Electron Devices, 2015, 62, (10), pp. 3348–3356 doi: i10.1109/TED.2015.2462743.
    2. 2)
      • 13. Saurabh, S., Kumar, M.J.: ‘Impact of strain on drain current and threshold voltage of nanoscale double gate tunnel field effect transistor: theoretical investigation and analysis’, Jpn. J. Appl. Phys., 2009, 48, (6R), pp. 064503-1–064503-7 doi: i10.1143/JJAP.48.064503.
    3. 3)
      • 15. Patel, N., Ramesha, A., Mahapatra, S.: ‘Drive current boosting of n-type tunnel FET with strained SiGe layer at source’, Microelectron. J., 2008, 39, (12), pp. 1671–1677 doi: i10.1016/j.mejo.2008.02.020.
    4. 4)
      • 18. Upasana, R.N., Gupta, M., Saxena, M.: ‘Simulation study for dual material gate hetero-dielectric TFET: static performance analysis for analog applications’. 2013 Annual IEEE India Conf. (INDICON), Mumbai, 2013, pp. 1–6, doi: 10.1109/INDCON.2013.6725867.
    5. 5)
      • 12. Dash, D.K., Saha, P., Sarkar, S.K.: ‘Analytical modeling of asymmetric hetero-dielectric engineered dual-material DG-TFET’, J. Comput. Electron., 2018, 17, (1), pp. 181–191 doi: i10.1007/s10825-017-1102-8.
    6. 6)
      • 6. Reddy, G.V., Kumar, M.J.: ‘A new dual-material double-gate (DMDG) nanoscale SOI MOSFET – two-dimensional analytical modeling and simulation’, IEEE Trans. Nanotechnol., 2005, 4, (2), pp. 260–268 doi: i10.1109/TNANO.2004.837845.
    7. 7)
      • 22. Trivedi, V.P., Fossum, J.G.: ‘Quantum-mechanical effects on the threshold voltage of undoped double-gate MOSFETs’, IEEE Electron Device Lett., 2005, 26, (8), pp. 579–582 doi: i10.1109/LED.2005.852741.
    8. 8)
      • 1. Upasana, R., Saxena, N.M., Gupta, M.: ‘Switching performance analyses of gate material and gate dielectric engineered TFET architectures and impact of interface oxide charges’. 2014 2nd Int. Conf. on Devices, Circuits and Systems (ICDCS), Coimbatore, 2014, pp. 1–6, doi: 10.1109/ICDCSyst.2014.6926182.
    9. 9)
      • 7. Mahajan, A., Dash, D.K, Banerjee, P., et al: ‘Analytical modeling of triple-metal hetero-dielectric DG SON TFET’, J. Mater. Eng. Perform., 2018, 27, (6), pp. 2693–2700 doi: i10.1007/s11665-018-3225-x.
    10. 10)
      • 2. Kumar, M.J., Janardhanan, S.: ‘Doping-less tunnel field effect transistor: design and investigation’, IEEE Trans. Electron Devices, 2013, 60, (10), pp. 3285–3290 doi: i10.1109/TED.2013.2276888.
    11. 11)
      • 16. Bagga, N., Sarkar, S.K.: ‘An analytical model for tunnel barrier modulation in triple metal double gate TFET’, IEEE Trans. Electron Devices, 2015, 62, (7), pp. 2136–2142 doi: i10.1109/TED.2015.2434276.
    12. 12)
      • 9. Honma, T., Sasaki, I., Tamura, N.: ‘Fabrication of functionally graded SiO2-Mo material by centrifugation and Floc-casting of highly concentrated slurry’, Int. J. Appl. Ceram. Technol., 2013, 10, (2), pp. 348–353 doi: i10.1111/j.1744-7402.2011.02746.x.
    13. 13)
      • 8. Saha, P., Sarkhel, S., Sarkar, S.K: ‘3D modeling and performance analysis of dual material Tri-gate tunnel field effect transistor’, IETE Tech. Rev., 2019, 36, (2), pp. 117–129 doi: i10.1080/02564602.2018.1428503.
    14. 14)
      • 5. Deb, S., Singh, N.B., Islam, N., et al: ‘Work function engineering with linearly graded binary metal alloy gate electrode for short-channel SOI MOSFET’, IEEE Trans. Nanotechnol., 2012, 11, (3), pp. 472–478 doi: i10.1109/TNANO.2011.2177669.
    15. 15)
      • 4. Abdi, D.B., Jagadesh Kumar, M.: ‘Controlling ambipolar current in tunneling FETs using overlapping gate-on-drain’, IEEE J. Electron Devices Soc., 2014, 2, (6), pp. 187–190 doi: i10.1109/JEDS.2014.2327626.
    16. 16)
      • 21. Kwon, D.W., Kim, H.W., Kim, J.H., et al: ‘Effects of localized body doping on switching characteristics of tunnel FET inverters with vertical structures’, IEEE Trans. Electron Devices, 2017, 64, (4), pp. 1799–1805 doi: i10.1109/TED.2017.2669365.
    17. 17)
      • 23. Vishnoi, R., Kumar, M.J.: ‘An accurate compact analytical model for the drain current of a TFET from subthreshold to strong inversion’, IEEE Trans. Electron Devices, 2015, 62, (2), pp. 478–484 doi: i10.1109/TED.2014.2381560.
    18. 18)
      • 10. Choi, Y.-H., Bulliard, X., Benayad, A., et al: ‘Design and fabrication of compositionally graded inorganic oxide thin films: mechanical, optical and permeation characteristics’, Acta Mater., 2010, 58, pp. 6495–6503 doi: i10.1016/j.actamat.2010.08.011.
    19. 19)
      • 3. Choi, W.Y., Park, B.-G., Lee, J.D., et al: ‘Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec’, IEEE Electron Device Lett., 2007, 28, (8), pp. 743–745 doi: i10.1109/LED.2007.901273.
    20. 20)
      • 14. Kumari, T., Saha, P., Dash, D.K, et al: ‘Modeling of dual gate material hetero-dielectric strained PNPN TFET for improved ON current’, J. Mater. Eng. Perform., 2018, 27, (6), pp. 2747–2753 doi: i10.1007/s11665-018-3144-x.
    21. 21)
      • 17. Kumar, S., Goel, E., Singh, K., et al: ‘2-D analytical modeling of the electrical characteristics of dual-material double-gate TFETs with a SiO2/HfO2 stacked gate-oxide structure’, IEEE Trans. Electron Devices, 2017, 64, (3), pp. 960–968 doi: i10.1109/TED.2017.2656630.
    22. 22)
      • 24. Kolkovsky, K., Lukat, E.K., Kunath, C.: ‘Reactively sputtered hafnium oxide on silicon dioxide: structural and electrical properties’, Solid-State Electron., 2015, 106, pp. 63–67 doi: i10.1016/j.sse.2015.01.004.
    23. 23)
      • 20. Young, K.K.: ‘Short channel effect in fully depleted SOI MOSFETs’, IEEE Trans. Electron Devices, 1989, 36, (2), pp. 399–402 doi: i10.1109/16.19942.
    24. 24)
      • 11. Giannatsis, J., Vassilakos, A., Canellidis, V., et al: ‘Fabrication of graded structures by extrusion 3D printing’, 2015, pp. 175–179, 10.1109/IEEM.2015.7385631.
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