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access icon free Impact of PZT gate-stack induced negative capacitance on analogue/RF figures-of-merits of electrostatically-doped ferroelectric Schottky-barrier tunnel FET

In this work, the authors investigate analogue and radio-frequency (RF) figures-of-merit (FOM) of electrostatically-doped ferroelectric Schottky-barrier tunnel field-effect transistor (FET) (ED-FE-SBTFET) by deploying PZT (lead zirconium titanate) gate stack and dopant-free technology. This PZT gate stack results in negative capacitance behaviour as a result of the positive feedback among the electric dipoles within it. It realises an intrinsic amplifier to amplify the surface potential due to the applied gate bias and enhances the gate controllability significantly. As a result it facilitates lower ambipolar current, considerably high drive current and faster switching transitions. As the structure is realised by using dopant-free technique it ensures simplified fabrication process as it avoids the need of ion implantation and thermal annealing, reduces thermal budget. Here, a detailed comparison is carried-out between charge plasma Schottky-barrier tunnel FET and ED-FE-TFET for their high frequency FOMs such as cut-off frequency (), gain bandwidth product, transconductance generation factor and so on. The higher ratio of ED-FE-SBTFET reduces the static and dynamic both types of powers in digital circuits, while higher ratio ensures lower bias power of an amplifier.


    1. 1)
      • 7. Singh, S., Sinha, R., Kondekar, P.N.: ‘A novel ultra steep dynamically reconfigurable electrostatically doped silicon nanowire Schottky barrier FET’, Superlattices Microstruct., 2016, 93, pp. 4049.
    2. 2)
      • 3. Jhaveri, R., Nagavarapu, V., Woo, J.: ‘Asymmetric Schottky tunneling source SOI MOSFET design for mixed-mode applications’, IEEE Trans. Electron Devices, 2009, 56, (1), pp. 9399.
    3. 3)
      • 2. Jhaveri, R., Woo, J.: ‘Schottky tunneling source MOSFET design for mixed mode and analog applications’. Proc. of the 36th IEEE European Solid-State Device Research Conf., (ESSDERC), Montreux, 2006, pp. 295298.
    4. 4)
      • 15. Madan, J., Gupta, R.S., Chaujar, R.: ‘Performance investigation of heterogeneous gate dielectric-gate metal engineered–gate all around-tunnel FET for RF applications’. Microsystem Technologies, 2016, pp. 110.
    5. 5)
      • 21. Biswas, K., Sarkar, A., Sarkar, C.K.: ‘Spacer engineering for performance enhancement of junctionless accumulation-mode bulk FinFETs’, IET Circuits Devices Syst., 2017, 11, (1), pp. 8088.
    6. 6)
      • 17. Mohapatra, S.K., Pradhan, K.P., Artola, L., et al: ‘Estimation of analog/RF figures-of-merit using device design engineering in gate stack double gate MOSFET’, Mater. Sci. Semicond. Process., 2015, 31, pp. 455462.
    7. 7)
      • 8. Singh, S., Singh, A.P., Kondekar, P.N.: ‘A novel self-aligned charge plasma Schottky barrier tunnel FET using work function engineering’, Microelectron. Eng., 2017, 168, pp. 6775.
    8. 8)
      • 22. ATLAS Device Simulation Soft, Silvaco, Santa Clara, CA, USA, 2012.
    9. 9)
      • 23. Patil, G.C., Qureshi, S.: ‘A comparative study on analog/RF performance of Pt-germanide and Pt-silicide Schottky barrier pMOSFETs’. 2012 IEEE Int. Conf. on Electron Devices and Solid State Circuit (EDSSC), Bangkok, Thailand, 2012, pp. 12.
    10. 10)
      • 27. Ytterdal, T., Cheng, Y., Fjeldly, T.A.: ‘Device modeling for analog and RF CMOS circuit design’ (John Wiley & Sons, Chichester, England, 2003).
    11. 11)
      • 16. Valentin, R., Dubois, E., Raskin, J.P., et al: ‘RF small-signal analysis of Schottky-barrier p-MOSFET’, IEEE Trans. Electron Devices, 2008, 55, (5), pp. 11921202.
    12. 12)
      • 10. Zhirnov, V.V., Cavin, R.K.: ‘Nanoelectronics: negative capacitance to the rescue?’, Nat. Nanotechnol., 2008, 3, (2), pp. 7778.
    13. 13)
      • 14. Sivaram, G.S., Chakraborty, S., Das, R., et al: ‘Impact of lateral straggle on the analog/RF performance of asymmetric gate stack double gate MOSFET’, Superlattices Microstruct., 2016, 97, pp. 477488.
    14. 14)
      • 1. Wilson, L.: ‘International technology roadmap for semiconductors (ITRS)’ (Semiconductor Industry Association, USA, 2013). Available at
    15. 15)
      • 24. Kang, I.M., Shin, H.: ‘Non-quasi-static small-signal modeling and analytical parameter extraction of SOI FinFETs’, IEEE Trans. Nanotechnol., 2006, 5, (3), pp. 205210.
    16. 16)
      • 6. Singh, S., Pal, P., Kondekar, P.N.: ‘Charge-plasma-based super-steep negative capacitance junctionless tunnel field effect transistor: design and performance’, IET Electron. Lett., 2014, 50, (25), pp. 19631964.
    17. 17)
      • 19. Pradhan, K.P., Mohapatra, S.K., Sahu, P.K., et al: ‘Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET’, Microelectron. J., 2014, 45, (2), pp. 144151.
    18. 18)
      • 5. Guin, S., Chattopadhyay, A., Karmakar, A., et al: ‘Impact of a pocket doping on the device performance of a Schottky tunneling field-effect transistor’, IEEE Trans. Electron Devices, 2014, 61, (7), pp. 25152522.
    19. 19)
      • 25. Koley, K., Syamal, B., Kundu, A., et al: ‘Subthreshold analog/RF performance of underlap DG FETs with asymmetric source/drain extensions’, Microelectron. Reliab., 2012, 52, (11), pp. 25722578.
    20. 20)
      • 26. Tsividis, Y., McAndrew, C.: ‘Operation and modeling of the MOS transistor’, vol. 2, (Oxford University Press, New York, 1999).
    21. 21)
      • 9. Salahuddin, S., Datta, S.: ‘Use of negative capacitance to provide voltage amplification for low power nanoscale devices’, Nano Lett., 2008, 8, (2), pp. 405410.
    22. 22)
      • 11. Khan, A.I., Yeung, C.W., Hu, C., et al: ‘Ferroelectric negative capacitance MOSFET: capacitance tuning & antiferroelectric operation’. IEEE Int. Electron Devices Meeting (IEDM), Washington, DC, USA, 2011, pp. 11(1)11(3).
    23. 23)
      • 12. Lee, M.H., Lin, J.C., Wei, Y.T., et al: ‘Ferroelectric negative capacitance hetero-tunnel field-effect-transistors with internal voltage amplification’. IEEE Int. Electron Devices Meeting (IEDM), Washington, DC, USA, 2013.
    24. 24)
      • 18. Sahu, P.K., Mohapatra, S.K., Pradhan, K.P.: ‘Zero temperature-coefficient bias point over wide range of temperatures for single-and double-gate UTB-SOI n-MOSFETs with trapped charges’, Mater. Sci. Semicond. Process., 2015, 31, pp. 175183.
    25. 25)
      • 4. Zhang, M., Knoch, J., Zhao, Q.T., et al: ‘Schottky barrier height modulation using dopant segregation in Schottky-barrier SOI-MOSFETs’. Proc. of 35th European IEEE Solid-State Device Research Conf., Grenoble, France, 2005, pp. 457460.
    26. 26)
      • 13. Singh, S., Kondekar, P.N.: ‘A novel electrostatically doped ferroelectric Schottky barrier tunnel FET: process resilient design’, J. Comput. Electron., 2017, 16, (3), pp. 685695.
    27. 27)
      • 20. Kumar, M., Haldar, S., Gupta, M., et al: ‘Impact of gate material engineering (GME) on analog/RF performance of nanowire Schottky-barrier gate all around (GAA) MOSFET for low power wireless applications: 3D T-CAD simulation’, Microelectron. J., 2014, 45, (11), pp. 15081514.

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