Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

access icon free 0.1–5 GHz wideband ΔΣ fractional-N frequency synthesiser for software-defined radio application

This article proposes a wideband ΔΣ fractional-N frequency synthesiser (WBFS) for software-defined radio application. The frequency synthesiser has two modes: the regular mode with low phase noise performance and the low-power mode for the low-power applications at lower frequency band. The authors also propose adjustable replica (AR) bias circuit for the frequency selection multiplexer (FSMUX) in the divide-by-two divider chain to optimise the power consumption at different frequencies while keep the output swing constant at different bias current to achieve robust operation. The FSMUX is implemented in differential structure instead of the widely used quadrature structure to reduce power and area especially at high carrier frequency. Implemented in 65 nm CMOS process with a 1.2-V supply, the WBFS generates frequency from 0.1 to 5 GHz. The maximum power at regular and low-power mode is 21 and 10.2 mW, respectively. The phase noise is −120.3 dBc/Hz at 1 MHz offset (2.75375 GHz) at regular mode and −122.8 dBc/Hz at 1 MHz offset (1.3525 GHz) at low-power mode. Thanks to the differential FSMUX with the proposed AR bias circuit and the low-power mode, the WBFS power is significantly reduced, compared with that of the prior WBFS with comparable frequency range.

References

    1. 1)
      • 5. Lou, W., Liu, X., Feng, P., et al: ‘An integrated 0.38–6 GHz, 9–12 GHz fully differential fractional-N frequency synthesizer for multi-standard reconfigurable MIMO communication application’, Analog Integr. Circ. Sig. Process., 2014, 78, (3), pp. 807817.
    2. 2)
      • 14. Zhang, Z., Liu, L., Feng, P., et al: ‘A 2.4–3.6-GHz wideband subharmonically injection-locked PLL with adaptive injection timing alignment technique’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2017, 25, (3), pp. 929941.
    3. 3)
      • 15. Lu, L., Chen, J., Yuan, L., et al: ‘An 18 mW 1.175-to-2 GHz frequency synthesizer with a constant loop bandwidth for DVB-T tuner’, IEEE Trans. Micro. Theory Tech., 2009, 57, (4), pp. 928937.
    4. 4)
      • 12. Yu, X., Han, S., Jin, Z., et al: ‘A class-C VCO based Σ-Δ fractional-N frequency synthesizer with AFC for 802.11ah applications’, J. Semicond., 2015, 36, (9), p. 095003.
    5. 5)
      • 18. Azadbakht, M., Sahafi, A., Aghdam, E.N.: ‘A dual band fractional-N frequency synthesizer with a self-calibrated charge pump for WLAN standards’, J. Circuits Syst. Comput., 2018, 27, (8), p. 1850131.
    6. 6)
      • 13. Aparicio, R., Hajimiri, A.: ‘Concepts and methods in optimization of integrated LC VCOs’, IEEE J. Solid-State Circuits, 2001, 36, (6), pp. 896909.
    7. 7)
      • 7. Rong, S., Yin, J., Luong, H.: ‘A 0.05- to 10-GHz, 19- to 22-GHz, and 38- to 44-GHz frequency synthesizer for software-defined radios in 0.13-μm CMOS process’, IEEE Trans. Circuits Syst. II Express Briefs., 2016, 63, (1), pp. 109113.
    8. 8)
      • 16. Shu, K., Sánchez-Sinencio, E.: ‘CMOS PLL synthesizers: analysis and design’ (Springer Science and Business Media Press, USA, 2005).
    9. 9)
      • 2. Kuang, X., Wu, N.: ‘A fast-settling PLL frequency synthesizer with direct frequency presetting’. IEEE ISSCC Digest of Technical Papers, San Francisco, CA, USA, February 2006, pp. 741750.
    10. 10)
      • 10. Zahir, Z., Banerjee, G.: ‘A 0.9–5.4 GHz wideband fast settling frequency synthesizer for 5G based consumer services’, Analog Integr. Circ. Sig. Process., 2018, 97, (3), pp. 565577, https://doi.org/10.1007/s10470-018-1312-4.
    11. 11)
      • 9. Cai, Q., Yang, Z., Zhang, M., et al: ‘A fast-settling charge-pump PLL with constant loop bandwidth’, Analog Integr. Circ. Sig. Process., 2018, 94, (1), pp. 1926.
    12. 12)
      • 4. Zhou, J., Li, W., Huang, D., et al: ‘A 0.4–6-GHz frequency synthesizer using dual-mode VCO for software-defined radio’, IEEE Trans. Micro. Theory Tech., 2013, 61, (2), pp. 848859.
    13. 13)
      • 3. Zhang, Z., Yang, J., Liu, L., et al: ‘A 1.25-to-6.25 GHz −237.2-dB FOM wideband self-biased PLL for multi-rate serial link data transmitter’, IEICE Electron. Express, 2017, 14, (11), pp. 18.
    14. 14)
      • 11. Zhang, Z., Yang, J., Liu, L., et al: ‘A 0.1-to-5 GHz wideband ΔΣ fractional-N frequency synthesizer for software-defined radio application’. IEEE Int. Conf. on Solid-State and Integ. Circ. Tech. (ICSICT), Hangzhou, China, October 2016, pp. 15701572.
    15. 15)
      • 8. Deng, W., Hara, A., Okada, K., et al: ‘A compact and low-power fractionally injection-locked quadrature frequency synthesizer using a self-synchronized gating injection technique for software-defined radios’, IEEE J. Solid-State Circuits, 2014, 49, (9), pp. 19841994.
    16. 16)
      • 6. Lo, Y.-C., Rashidi, N., Hwang, Y.-H., et al: ‘A 0.6 ps jitter 2–16 GHz 130 nm CMOS frequency synthesizer for broadband applications’. Proc. of IEEE ISCAS, Lisbon, Portugal, May 2015, pp. 30483051.
    17. 17)
      • 17. Razavi, B.: ‘Phase-locking in wireline systems: present and future’. IEEE CICC, San Jose, USA, September 2008, pp. 615622.
    18. 18)
      • 1. Elkholy, A., Saxena, S., Okada, K., et al: ‘A 2.0–5.5 GHz wide bandwidth ring-based digital fractional-N PLL with extended range multi-modulus divider’, IEEE J. Solid-State Circuits, 2016, 51, (8), pp. 17711784.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2018.5271
Loading

Related content

content/journals/10.1049/iet-cds.2018.5271
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address