access icon free Single bit-line 8T SRAM cell with asynchronous dual word-line control for bit-interleaved ultra-low voltage operation

This study proposes a single bit-line and disturbance-free static random-access memory (SRAM) cell for ultra-low voltage applications. SRAM cell with read-decoupled and cross-point structure addresses both the read-disturb and half-select stability issues; nevertheless, the write-ability is degraded due to the stacked pass transistors. In this study, the authors propose a single-ended 8T bit-cell and dual word-line control technique that can simultaneously improve the read stability, half-select stability, and write-ability without additional peripheral circuits, which is advantageous for bit-interleaved ultra-low voltage operations. A 4 kb test chip was implemented in a 90 nm complementary metal–oxide–semiconductor process to verify the proposed design. Silicon measurements indicate that the proposed design can operate at a voltage as low as 360 mV with 2.68 μW power consumption.

Inspec keywords: control engineering computing; asynchronous machines; CMOS integrated circuits; SRAM chips; machine control; integrated circuit design; low-power electronics

Other keywords: ingle-ended 8T bit-cell; ultra-low voltage; random-access memory cell; bit-interleaved ultra-low voltage operation; half-select stability; dual word-line control; read stability; asynchronous dual word-line control; single bit-line 8T SRAM cell; metal–oxide–semiconductor process; write-ability

Subjects: Power system control; Control of electric power systems; Control engineering computing; Semiconductor storage; Memory circuits; CMOS integrated circuits; Asynchronous machines; Digital circuit design, modelling and testing

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