http://iet.metastore.ingenta.com
1887

Single bit-line 8T SRAM cell with asynchronous dual word-line control for bit-interleaved ultra-low voltage operation

Single bit-line 8T SRAM cell with asynchronous dual word-line control for bit-interleaved ultra-low voltage operation

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Circuits, Devices & Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

This study proposes a single bit-line and disturbance-free static random-access memory (SRAM) cell for ultra-low voltage applications. SRAM cell with read-decoupled and cross-point structure addresses both the read-disturb and half-select stability issues; nevertheless, the write-ability is degraded due to the stacked pass transistors. In this study, the authors propose a single-ended 8T bit-cell and dual word-line control technique that can simultaneously improve the read stability, half-select stability, and write-ability without additional peripheral circuits, which is advantageous for bit-interleaved ultra-low voltage operations. A 4 kb test chip was implemented in a 90 nm complementary metal–oxide–semiconductor process to verify the proposed design. Silicon measurements indicate that the proposed design can operate at a voltage as low as 360 mV with 2.68 μW power consumption.

References

    1. 1)
      • 1. Myers, J., Savanth, A., Gaddh, R., et al: ‘A subthreshold ARM cortex-M0 + subsystem in 65 nm CMOS for WSN applications with 14 power domains, 10T SRAM, and integrated voltage regulator’, IEEE J. Solid-State Circuits, 2016, 51, (1), pp. 3144.
    2. 2)
      • 2. Lutkemeier, S., Jungeblut, T., Berge, H.K.O., et al: ‘A 65 nm 32 b subthreshold processor with 9T multi-Vt SRAM and adaptive supply voltage control’, IEEE J. Solid-State Circuits, 2013, 48, (1), pp. 819.
    3. 3)
      • 3. Alioto, M.: ‘Ultra-low power VLSI circuit design demystified and explained: a tutorial’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2012, 59, (1), pp. 329.
    4. 4)
      • 4. Verma, N., Chandrakasan, A.P.: ‘A 256 kb 65 nm 8T subthreshold sram employing sense-amplifier redundancy’, IEEE J. Solid-State Circuits, 2008, 43, (1), pp. 141149.
    5. 5)
      • 5. Kim, T.H., Liu, J., Kim, C.H.: ‘A voltage scalable 0.26 V, 64 kb 8 T SRAM with vmin lowering techniques and deep sleep mode’, IEEE J. Solid-State Circuits, 2009, 44, (6), pp. 17851795.
    6. 6)
      • 6. Chang, M.H., Chiu, Y.T., Hwang, W.: ‘Design and Iso-area vmin analysis of 9T subthreshold SRAM with bit-interleaving scheme in 65-nm CMOS’, IEEE Trans. Circuits Syst. II, Exp. Briefs, 2012, 59, (7), pp. 429433.
    7. 7)
      • 7. Tu, M.H., Lin, J.Y., Tsai, M.C., et al: ‘A single-ended disturb-free 9T subthreshold SRAM with cross-point data-aware write word-line structure, negative bit-line, and adaptive read operation timing tracing’, IEEE J. Solid-State Circuits, 2012, 47, (6), pp. 14691482.
    8. 8)
      • 8. Chiu, Y.W., Hu, Y.H., Zhao, J.K., et al: ‘A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist’. Proc. Int. Symp. Low Power Electron. Design (ISLPED), Beijing, China, September 2013, pp. 5156.
    9. 9)
      • 9. Chiu, Y.W., Hu, Y.H., Tu, M.H., et al: ‘40 nm bit-interleaving 12 T subthreshold SRAM with data-aware write-assist’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2014, 61, (9), pp. 25782585.
    10. 10)
      • 10. Lu, C.Y., Tu, M.H., Yang, H.I., et al: ‘A 0.33-V, 500-kHz, 3.94-uW 40-nm 72-Kb 9 T subthreshold SRAM with ripple bit-line structure and negative bit-line write-assist’, IEEE Trans. Circuits Syst. II, Exp. Briefs, 2012, 59, (12), pp. 863867.
    11. 11)
      • 11. Lu, C.Y., Chuang, C.T., Jou, S.J., et al: ‘A 0.325 V, 600-kHz, 40-nm 72-kb 9T subthreshold SRAM with aligned boosted write wordline and negative write bitline write-assist’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2015, 23, (5), pp. 958962.
    12. 12)
      • 12. Zimmer, B., Seng Oon, T., Huy, V., et al: ‘SRAM assist techniques for operation in a wide voltage range in 28-nm CMOS’, IEEE Trans. Circuits Syst. II, Exp. Briefs, 2012, 59, (12), pp. 853857.
    13. 13)
      • 13. Chang, M.F., Chang, S.W., Chou, P.W., et al: ‘A 130 mV SRAM with expanded write and read margins for subthreshold applications’, IEEE J. Solid-State Circuits, 2011, 46, (2), pp. 520529.
    14. 14)
      • 14. Teman, A., Pergament, L., Cohen, O., et al: ‘A 250 mV 8 kb 40 nm ultra-low power 9T supply feedback SRAM (SF-SRAM)’, IEEE J. Solid-State Circuits, 2011, 46, (11), pp. 27132726.
    15. 15)
      • 15. Kushwah, C.B., Vishvakarma, S.K.: ‘A single-ended with dynamic feedback control 8T subthreshold SRAM cell’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2016, 24, (1), pp. 373377.
    16. 16)
      • 16. Saeidi, R., Sharifkhani, M., Hajsadeghi, K.: ‘A subthreshold symmetric SRAM cell with high read stability’, IEEE Trans. Circuits Syst. II, Exp. Briefs, 2014, 61, (1), pp. 2630.
    17. 17)
      • 17. Yang, Y., Jeong, H., Song, S.C., et al: ‘Single bit-line 7T SRAM cell for near-threshold voltage operation with enhanced performance and energy in 14 nm FinFET technology’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2016, 63, (7), pp. 10231032.
    18. 18)
      • 18. Ickes, N., Gammie, G., Sinangil, M.E., et al: ‘A 28 nm 0.6 V low power DSP for mobile applications’, IEEE J. Solid-State Circuits, 2012, 47, (1), pp. 3546.
    19. 19)
      • 19. Toh, S.O., Guo, Z., Liu, T.J.K., et al: ‘Characterization of dynamic SRAM stability in 45 nm CMOS’, IEEE J. Solid-State Circuits, 2011, 46, (11), pp. 27022712.
    20. 20)
      • 20. Kim, D., Chandra, V., Aitken, R., et al: ‘Variation-aware static and dynamic writability analysis for voltage-scaled bit-interleaved 8-T SRAMs’. Proc. IEEE Int. Symp. Low Power Electron. Design, Fukuoka, Japan, August 2011, pp. 145150.
    21. 21)
      • 21. Wang, J., Nalam, S., Calhoun, B.H.: ‘Analyzing static and dynamic write margin for nanometer SRAMs’. Proc. IEEE Int. Symp. Low Power Electron. Design (ISLPED), Bangalore, India, August 2008, pp. 129134.
    22. 22)
      • 22. Rooseleer, B., Cosemans, S., Dehaene, W.: ‘A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, ultra low leakage power memory using dynamic cell stability and a dual swing data link’, IEEE J. Solid-State Circuits, 2012, 47, (7), pp. 17841796.
    23. 23)
      • 23. Kushida, K., Suzuki, A., Fukano, G., et al: ‘A 0.7 V single-supply SRAM with 0.495 um2 cell in 65 nm technology utilizing self-write-back sense amplifier and cascaded bit line scheme’, IEEE J. Solid-State Circuits, 2009, 44, (4), pp. 11921198.
    24. 24)
      • 24. Cosemans, S., Dehaene, W., Catthoor, F.: ‘A low-power embedded SRAM for wireless applications’, IEEE J. Solid-State Circuits, 2007, 42, (7), pp. 16071617.
    25. 25)
      • 25. Yamaoka, M., Osada, K., Kawahara, T.: ‘A cell-activation-time controlled SRAM for low-voltage operation in DVFS SoCs using dynamic stability analysis’. Proc. European Solid-State Circuits Conf. (ESSCIRC), Edinburgh, UK, September 2008, pp. 286289.
    26. 26)
      • 26. Makino, H., Nakata, S., Suzuki, H., et al: ‘Reexamination of SRAM cell write margin definitions in view of predicting the distribution’, IEEE Trans. Circuits Syst. II, Exp. Briefs, 2011, 58, (4), pp. 230234.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2018.5150
Loading

Related content

content/journals/10.1049/iet-cds.2018.5150
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address