Low leakage domino logic circuit for wide fan-in gates using CNTFET

Low leakage domino logic circuit for wide fan-in gates using CNTFET

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A carbon nanotube field effect transistor (CNTFET) emerged as an alternative to the complementary metal oxide semiconductor (CMOS) for implementing low-power high-speed very-large-scale integration circuits. In this study, the CNTFET technology is discussed that has faster switching speed and high-carrier mobility as compared with the CMOS technology. A new technique ultra-low power dynamic node driven transistor domino logic is proposed for designing low-power domino logic circuits. 2, 4, 8 and 16 input logic gates are simulated using the proposed and existing techniques. Simulation is done on an H-Spice Stanford CNFET 32 nm model at a clock frequency of 200 MHz using the CNTFET technology. The proposed technique shows a maximum power reduction of 57.14% and a maximum delay reduction of 50.24% as compared with the current mirror footed domino logic technique in CNTFET technology. The proposed technique has a maximum power reduction of 96.61% in the CNTFET technology as compared with its counterpart in the CMOS technology for the two-input OR gate. The proposed technique shows a maximum improvement of 1.39× in unity noise gain as compared with the conditional stacked keeper domino logic technique for 16 input OR gates in the CNTFET technology at 200 MHz.


    1. 1)
      • 1. Anis, M., Areibi, S., Elmasry, M.: ‘Design and optimization of multi-threshold CMOS (MTCMOS) circuit’, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 2003, 22, (10), pp. 13241342.
    2. 2)
      • 2. Roy, K., Mukhopadhyay, S., Mahmoodi, H.: ‘Leakage current mechanisms and leakage reduction techniques in deep-submicron CMOS circuits’, Proc. IEEE, 2003, 91, (2), pp. 305327.
    3. 3)
      • 3. Dadashi, A., Mirmotahari, O., Berg, Y.: ‘NP domino, ultra-Low-voltage, high-speed, dual-rail, CMOS NOR gates’, Circuits Syst., 2016, 7, (8), pp. 19161926.
    4. 4)
      • 4. Peiravi, A., Asyaei, M.: ‘Robust low leakage controlled keeper by current-comparison domino for wide fan-in gates, integration’, VLSI J., 2012, 45, (1), pp. 2232.
    5. 5)
      • 5. Moaiyeri, M. H., Razi, F.: ‘Performance analysis and enhancement of 10-nm GAA CNTFET-based circuits in the presence of CNT-metal contact resistance’, J. Comput. Electron., 2017, 16, (2), pp. 240252.
    6. 6)
      • 6. Kaushik, B. K., Majumder, M.K.: ‘Carbon nanotube-based VLSI interconnects’, Springer Briefs in Applied Sciences and Technology, (Springer, India, 2015), ch. 2, pp. 1737.
    7. 7)
      • 7. Javey, A., Kong, J.: ‘Carbon nanotube electronics’ in ‘Integrated circuits and Systems’ (Springer, Springer, USA, 2009), pp 120ISBN 978-0-387-69285-2.
    8. 8)
      • 8. Qin, L.C.: ‘Determination of the chiral indices (n,m) of carbon nanotubes by electron diffraction’, Phys. Chem. Chem. Phys., 2007, 9, (1), pp. 3148.
    9. 9)
      • 9. Bozorgmehr, A., Moaiyeri, M. H., Navi, K., et al: ‘Ultra-efficient fuzzy min/max circuits based on carbon nanotube FETs’, IEEE Trans. Fuzzy Syst., 2018, 26, (2), pp. 10731078.
    10. 10)
      • 10. Wang, X., Qunqing, L., Jing, X., et al: ‘Fabrication of ultralong and electrically uniform single-walled carbon nanotubes on clean substrates’, Nano Lett., 2009, 9, (9), pp. 31373141.
    11. 11)
      • 11. Aravind, S., Shravan, S., Shrijan, S., et al: ‘Simulation of carbon nanotube field effect transistors using NEGF’. IOP Conf. Series: Materials Science and Engineering, IconAMMA, 2016, Bangalore, India, 14–16 July 2016.
    12. 12)
      • 12. Peng, L.M., Zhang, Z., Wang, S.: ‘Carbon nanotube electronics: recent advances’, Mater. Today, 2014, 17, (9), pp. 433442.
    13. 13)
      • 13. Meter, J.V.: ‘Characterization of Schottky barrier carbon nanotube transistors and their applications to digital circuit design’ (Massachusetts Institute of Technology, Cambridge, MA, USA, 1979). Available at
    14. 14)
      • 14. Moghaddam, M., Moaiyeri, M. H., Eshghi, M.: ‘Design and evaluation of an efficient Schmitt trigger-based hardened latch in CNTFET technology’, IEEE Trans. Device Mater. Reliab., 2017, 17, (1), pp. 267277.
    15. 15)
      • 15. Moaiyeri, M. H., Doostaregan, A., Navi, K.: ‘Design of energy-efficient and robust ternary circuits for nanotechnology’, IET Circuits Devices Syst., 2011, 5, (4), pp. 285296.
    16. 16)
      • 16. Deng, J.: ‘A compact SPICE model for carbon-nanotube field-effect transistors including non-idealities and its application—part I: model of the intrinsic channel region’, IEEE Trans. Electron Devices, 2007, 54, (12), pp. 31863194.
    17. 17)
      • 17. Model File: Available at
    18. 18)
      • 18. Nan, L., XiaoXin, C., Kai, L., et al: ‘Low power adiabatic logic based on FinFETs’, Sci. China, 2014, 57, (2), pp. 113.
    19. 19)
      • 19. Muralidharan, J., Manimegalai, P.: ‘Current comparison domino based CHSK domino logic technique for rapid progression and Low power alleviation’, Int. J. Electr. Comput. Eng., 2017, 7, (5), pp. 24682473.
    20. 20)
      • 20. Mahmoodi, H., Roy, K.: ‘Diode footed domino: A leakage tolerant high fan-in dynamic circuit design style’, IEEE Trans. Circuits Syst., 2004, 51, (3), pp. 495503.
    21. 21)
      • 21. Cheng, C. H., Chang, S. C., Wang, J. S., et al: ‘Charge sharing fault detection for CMOS domino logic circuits’. Int. Symp. on Defect and Fault Tolerance in VLSI Systems, DFT'99, Albuquerque, New Mexico, 1–3 November 1999.
    22. 22)
      • 22. Gupta, T.K, Khare, K.: ‘Lector with footed-diode inverter: A technique for leakage reduction in domino circuits’, Circ. Syst. Signal Process., 2013, 32, (6), pp. 27072722.
    23. 23)
      • 23. Gupta, T.K., Pandey, A.K., Meena, O.P.: ‘Analysis and design of lector-based dual-Vt domino logic with reduced leakage current’, Circuit World, 2017, 43, (3), pp. 97104.
    24. 24)
      • 24. Moradi, F., Cao, T. V., Vatajelu, E. I., et al: ‘Domino logic designs for high-performance and leakage tolerant applications’, Integr. VLSI J., 2013, 46, (3), pp. 247254.
    25. 25)
      • 25. Peiravi, A., Asyaei, M.: ‘Current-comparison-based domino: new low-leakage high-speed domino circuit for wide fan-in gates’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2013, 21, (5), pp. 934943.
    26. 26)
      • 26. Gong, N., Guo, B., Lou, J., et al: ‘Analysis and optimization of leakage current characteristics in sub-65 nm dual Vt footed domino circuits’, Microelectron. J., 2008, 39, pp. 11491155.
    27. 27)
      • 27. Moradi, F., Peiravi, A., Mahmoodi, H.: ‘A new leakage-tolerant design for high fan-in domino gates’. Proc. 16th Int. Conf. on Microelectronics, 2004, Tunisia, 6–8 December 2004.
    28. 28)
      • 28. Moradi, F., Mahmoodi, H., Peiravi, A.: ‘A high speed and leakage-tolerant domino logic for high fan-in gates’. Proc. 15th ACM Great Lakes Symp. on VLSI (GLSVLSI), 2005, Chicago, IL, USA, 17–19 April 2005.
    29. 29)
      • 29. Peiravi, A., Moradi, F., Wisland, D. T.: ‘Leakage tolerant, noise immune domino logic for circuit design in the ultra deep submicron CMOS technology for high fan-in gates’, J. Appl. Sci., 2009, 9, (2), pp. 392396.
    30. 30)
      • 30. Shanbhag, N., Soumyanath, K., Martin, S.: ‘Reliable low- power design in the presence of deep submicron noise’. Proc. Int. Symp. on Low Power Electronics and Design, 2000, Rapallo, Italy, 25–27 July 2000.

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