@ARTICLE{ iet:/content/journals/10.1049/iet-cds.2018.5112, author = {Nevena R. Brnović}, author = {Igor Djurović}, author = {Veselin N. Ivanović}, author = {Marko Simeunović}, keywords = {phase extraction;multiple-clock-cycle;PPS estimators;polynomial regression;TF representation;quasi-maximum likelihood algorithm;polynomial phase signals estimation;flexible clock-cycle;field programmable gate array circuit design;quasimaximum likelihood estimator core;QML algorithm;instantaneous frequency estimator;hardware design;time–frequency analysis;white Gaussian noise;software implementations;}, ISSN = {1751-858X}, language = {English}, abstract = {Flexible, multiple-clock-cycle, hardware design for the quasi-maximum likelihood (QML) algorithm core realisation for the polynomial phase signals (PPSs) estimation is proposed. The QML algorithm significantly outperforms existing PPS estimators in terms of accuracy. However, its practical applications require efficient software and hardware systems. The main challenges in the proposed hardware development with respect to existing systems for time–frequency (TF) analysis are realisation of TF representation based instantaneous frequency estimator, the polynomial regression, and phase extraction. The developed design is tested on a PPS corrupted by a white Gaussian noise and verified by a field programmable gate array circuit design. All implementation and verification details are provided along with the comparison of the results achieved by hardware and software implementations.}, title = {Hardware implementation of the quasi-maximum likelihood estimator core for polynomial phase signals}, journal = {IET Circuits, Devices & Systems}, issue = {2}, volume = {13}, year = {2019}, month = {March}, pages = {131-138(7)}, publisher ={Institution of Engineering and Technology}, copyright = {© The Institution of Engineering and Technology}, url = {https://digital-library.theiet.org/;jsessionid=a90aqmlm4otrf.x-iet-live-01content/journals/10.1049/iet-cds.2018.5112} }