%0 Electronic Article
%A Harjap Saini
%A Anu Gupta
%K constant power consumption design
%K size 180.0 nm
%K novel differential logic gate
%K n-bit inputs
%K highly regular structure
%K novel DPA immune design
%K evaluation path
%K propagation delay
%K differential power analysis method
%K voltage 1.8 V
%K basic gates
%K power supply
%K TowerJazz CMOS technology
%K AND–NAND design
%K strong salience strength
%K noninvasive side-channel attack
%K OR–NOR function
%K Cadence tool
%X Differential power analysis (DPA) method is frequently used for the non-invasive side-channel attack to hack into the system. This study proposes a novel DPA immune design of basic gates, which show the dense distribution of autocorrelation and strong salience strength around 60%. The design has a highly regular structure with exactly similar evaluation path for both differential outputs, AND–NAND, and OR–NOR which can be easily extended for n-bit inputs. The design effort is minimal as the structure is such that AND–NAND design can be used to obtain OR–NOR function by just changing the placement of inputs. These gates have 0.46× less propagation delay, and 3.7× higher power consumption in comparison to other published work. The designs are simulated using Cadence tool with TowerJazz CMOS 180 nm technology with a power supply of 1.8 V.
%@ 1751-858X
%T Constant power consumption design of novel differential logic gate for immunity against differential power analysis
%B IET Circuits, Devices & Systems
%D January 2019
%V 13
%N 1
%P 103-109
%I Institution of Engineering and Technology
%U https://digital-library.theiet.org/;jsessionid=1g6ex4m2tdyvf.x-iet-live-01content/journals/10.1049/iet-cds.2018.5093
%G EN