http://iet.metastore.ingenta.com
1887

14.5 fJ/conversion-step 9-bit 100-kS/s non-binary weighted dual capacitor array based area and energy efficient SAR ADC in 90 nm CMOS

14.5 fJ/conversion-step 9-bit 100-kS/s non-binary weighted dual capacitor array based area and energy efficient SAR ADC in 90 nm CMOS

For access to this article, please select a purchase option:

Buy article PDF
$19.95
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Circuits, Devices & Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

In this work, design technique and analysis of low-energy consumption successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. A dual capacitor array (CA) generates a digital-to-analogue reference voltage with increased accuracy. The CA supports multiple parallel operations to enhance conversion speed. Unit sized capacitors in CAs are few in number and present good capacitance density, thereby providing area efficiency and ease of routeing. A 9-bit SAR ADC using the proposed dual CA, implemented in a 90 nm CMOS process, has a small core area footprint of 0.00371 mm2. At a 1 V supply and 100 kS/s, the ADC achieves a signal-to-noise and distortion ratio of 53.55 dB and consumes 0.47 μW, resulting in a figure-of-merit of 14.5 fJ/conversion step.

References

    1. 1)
      • 1. Tang, H., Sun, Z.C., Chew, K.W.R., et al: ‘A 1.33 μW 8.02-ENOB 100 kS/s successive approximation ADC with supply reduction technique for implantable retinal prosthesis’, IEEE Trans. Biomed. Circuits Syst., 2014, 8, (6), pp. 844856.
    2. 2)
      • 2. Zhu, Z., Xiao, Y., Song, X.: ‘VCM-based monotonic capacitor switching scheme for SAR ADC’, Electron. Lett., 2013, 49, (5), pp. 327329.
    3. 3)
      • 3. Liu, S., Shen, Y., Zhu, Z.: ‘A 12-Bit 10 MS/s SAR ADC with high linearity and energy-efficient switching’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2016, 63, (10), pp. 16161627.
    4. 4)
      • 4. Harpe, P., Zhou, C., Bi, Y., et al: ‘A 26 μW 8 bit 10 MS/s asynchronous SAR ADC for low energy radios’, IEEE J. Solid-State Circuits, 2011, 46, (7), pp. 15851595.
    5. 5)
      • 5. Galton, I.: ‘Why dynamic-element-matching DACs work’, IEEE Trans. Circuits Syst. II, Express Briefs, 2010, 57, (2), pp. 6974.
    6. 6)
      • 6. Kamalinejad, P., Mirabbasi, S., Leung, V.C.: ‘An ultra-low-power SAR ADC with an area-efficient DAC architecture’. Proc. IEEE Int. Symp. of Circuits and Systems, Rio de Janeiro, May 2011, pp. 1316.
    7. 7)
      • 7. Gopal, H.V., Baghini, M.S.: ‘An ultra low-energy DAC for successive approximation ADCs’. Proc. IEEE Int. Symp. of Circuits and Systems, Paris, May 2010, pp. 33493352.
    8. 8)
      • 8. Chen, F., Chandrakasan, A.P., Stojanovic, V.: ‘A low-power area-efficient switching scheme for charge-sharing DACs in SAR ADCs’. Proc. IEEE Custom Integrated Circuits Conf., San Jose, CA, September 2010, pp. 14.
    9. 9)
      • 9. Jagadish, D.N., Bhat, M.S.: ‘Low energy and area efficient nonbinary capacitor array based SAR ADC’. Proc. Fifth Int. Symp. on Electronic System Design, Surathkal, Mangalore, December 2014, pp. 5457.
    10. 10)
      • 10. Jagadish, D.N., Tonse, L., Bhat, M.S.: ‘11.39 fJ/conversion-step 780 kS/s 8 bit switched capacitor-based area and energy-efficient successive approximation register ADC in 90 nm complementary metal-oxide-semiconductor’, IET Circuits, Devices Syst., 2018, 12, (3), pp. 249255.
    11. 11)
      • 11. Jukna, S.: ‘Boolean function complexity: advances and frontiers’ (Springer Science & Business Media, Berlin, 2012).
    12. 12)
      • 12. Van, E.M., van Tuijl, E., Geraedts, P., et al: ‘A 10-bit charge-redistribution ADC consuming 1.9 μW at 1 MS/s’, IEEE J. Solid-State Circuits, 2010, 45, (5), pp. 10071015.
    13. 13)
      • 13. Tai, H.-Y., Hu, Y.-S., Chen, H.-S., et al: ‘A 0.85 fJ/conversion-step 10 b 200 kS/s subranging SAR ADC in 40 nm CMOS’. Proc. IEEE Int. Solid-State Circuits Conf., San Francisco, CA, February 2014, pp. 196197.
    14. 14)
      • 14. Long, C., Xiyuan, T., Sanyal, A., et al: ‘A 10.5-b ENOB 645 nW 100 kS/s SAR ADC with statistical estimation based noise reduction’. Proc. IEEE Custom Integrated Circuits Conf., San Jose, CA, September 2015, pp. 14.
    15. 15)
      • 15. Zhu, Z., Liang, Y.: ‘A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18-μm CMOS for medical implant devices’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2015, 62, (9), pp. 21672176.
    16. 16)
      • 16. Bai, W., Zhu, Z.: ‘A 0.5-V 9.3-ENOB 68-nW 10-kS/s SAR ADC in 0.18-μm CMOS for biomedical applications’, Microelectron. J., 2017, 59, pp. 4046.
    17. 17)
      • 17. Ruoyu, X., Bing, L., Jie, Y.: ‘Digitally calibrated 768-kS/s 10-b minimum-size SAR ADC array with dithering’, IEEE J. Solid-State Circuits, 2012, 47, (9), pp. 21292140.
    18. 18)
      • 18. Zhu, Z., Qiu, Z., Liu, M., et al: ‘A 6-to-10-Bit 0.5-to-0.9 V reconfigurable 2 MS/s power scalable SAR ADC in 0.18 μm CMOS’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2015, 62, (3), pp. 689696.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2018.5067
Loading

Related content

content/journals/10.1049/iet-cds.2018.5067
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address